MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 19

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). In the 56F8123, after reset, each
pin must be configured for the desired function. The initialization software will configure each pin for the
function listed first for each pin, as shown in
Note: Signals in italics are not available in the 56F8123 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3
pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of
the pin, it will become an input if no other registers are changed.
Freescale Semiconductor
Preliminary
V
Signal Name
DDA_OSC_PLL
V
V
DDA_ADC
V
V
V
V
SSA_ADC
DD_IO
DD_IO
DD_IO
DD_IO
V
V
V
V
SS
SS
SS
SS
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Pin No.
20
48
59
42
41
11
17
44
60
39
6
Supply
Supply
Supply
Supply
Supply
Type
State During
Reset
56F8323 Technical Data, Rev. 17
Table
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage regulator, if
it is enabled.
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power supply.
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
Ground — These pins provide ground for chip logic and I/O drivers.
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
2-2. Any alternate functionality must be programmed.
Signal Description
Signal Pins
19