MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 84

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
6.4 Operating Mode Register
The reset state for MB will depend on the Flash secured state. See
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX
bit is not functional in this device since there is no external memory interface. For all other bits, see the
56F8300 Peripheral User Manual.
Note:
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RESET
Type
Bit
Reset Mode, which has two submodes:
— Total Reset Mode
— Core-Only Reset Mode
Run Mode
The primary mode of operation for this device, in which the 56800E controls chip operation
Debug Mode
56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs,
continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from
being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
Stop Mode
56800E, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped.
For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before
entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated
interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.
– 56800E Core and all peripherals are reset
– 56800E Core in reset, peripherals are active
– This mode is required to provide the on-chip Flash interface module time to load data from Flash
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
into FM registers.
R/W
15
NL
0
14
0
13
0
12
0
11
0
56F8323 Technical Data, Rev. 17
10
Figure 6-1 OMR
0
9
0
R/W
CM
8
0
R/W
XP
7
0
R/W
SD
6
0
R/W
5
R
0
Part 4.2
R/W
SA
4
0
R/W
and
EX
3
0
Freescale Semiconductor
Part 7
2
0
0
R/W
MB
1
X
for detailed
Preliminary
R/W
MA
0
0