MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 69

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.6.3
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.6.4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.5
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.6.6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.6.7
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
Freescale Semiconductor
Preliminary
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00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—
Bits 9–8
Reserved—Bits 7–6
SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—
Bits 5–4
SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits
3–2
SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—
Bits 1–0
56F8323 Technical Data, Rev. 17
Register Descriptions
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