MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 81

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.24
5.6.25
5.6.26
5.6.27
5.6.28
5.6.29
5.6.30
5.6.30.1
This read-only bit reflects the state of the interrupt to the 56800E core.
5.6.30.2
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
5.6.30.3
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Freescale Semiconductor
Preliminary
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•
•
•
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Base + $1D
RESET
Read
Write
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ITCN Control Register (ICTL)
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Interrupt (INT)—Bit 15
Interrupt Priority Level (IPIC)—Bits 14–13
Vector Number - Vector Address Bus (VAB)—Bits 12–6
INT
15
0
14
0
—Base + 17
—Base + 18
—Base + 19
—Base + 1A
—Base + 1B
—Base + 1C
IPIC
13
0
Figure 5-26 ITCN Control Register (ICTL)
12 11 10
1
0
56F8323 Technical Data, Rev. 17
0
VAB
9
0
8
0
7
0
6
0
INT_DIS
5
0
4
1
1
3
1
0
IRQA STATE
2
1
Register Descriptions
1
0
0
IRQA
EDG
0
0
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