MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 49

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MC56F8323VFB60

Manufacturer Part Number
MC56F8323VFB60
Description
IC MPU HYBRID DSP 32K 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8323VFB60

Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
For Use With
MC56F8323EVME - BOARD EVALUATION MC56F8323
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC56F8323VFB60
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Preliminary
GPIOB_PUR
GPIOB_DR
GPIOB_DDR
GPIOB_PER
GPIOB_IAR
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
GPIOA_PUR
GPIOA_DR
GPIOA_DDR
GPIOA_PER
GPIOA_IAR
GPIOA_IENR
GPIOA_IPOLR
GPIOA_IPR
GPIOA_IESR
GPIOA_PPMODE
GPIOA_RAWDATA
Register Acronym
Register Acronym
Table 4-21 GPIOA Registers Address Map
Table 4-22 GPIOB Registers Address Map
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Address Offset
Address Offset
(GPIOA_BASE = $00 F2E0)
(GPIOB_BASE = $00 F300)
56F8323 Technical Data, Rev. 17
Pull-up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
Interrupt Edge-Sensitive Register
Pull-up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Push-Pull Mode Register
Raw Data Input Register
Register Description
Register Description
Peripheral Memory Mapped Registers
0 x 00FF
0 x 0000
0 x 0000
0 x 00FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 00FF
0 x 0FFF
0 x 0000
0 x 0000
0 x 0FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0FFF
Reset Value
Reset Value
49

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