MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 93

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.5.8.5
This bit selects the alternate function for GPIOB0.
6.5.8.6
This bit selects the alternate function for GPIOA5.
6.5.8.7
This bit selects the alternate function for GPIOA4.
6.5.8.8
This bit selects the alternate function for GPIOA3.
6.5.8.9
This bit selects the alternate function for GPIOA2.
6.5.9
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
6.5.9.1
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
Freescale Semiconductor
Preliminary
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Base + $C
RESET
Read
Write
0 = SS0 (default)
1 = TXD1
0 = PWMA5
1 = SCLK1
0 = PWMA4
1 = MOS1
0 = PWMA3
1 = MISO1
0 = PWMA2
1 = SS1
Peripheral Clock Enable Register (SIM_PCE)
GPIOB0 (B0)—Bit 4
GPIOA5 (A5)—Bit 3
GPIOA4 (A4)—Bit 2
GPIOA3 (A3)—Bit 1
GPIOA2 (A2)—Bit 0
Reserved—Bits 15–14
15
1
1
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
14
1
1
ADCA
13
1
CAN
12
1
11
1
1
56F8323 Technical Data, Rev. 17
DEC0
10
1
9
1
1
TMRC
8
1
7
1
1
TMRA
6
1
SCI 1 SCI 0
5
1
4
1
SPI1
3
1
SPI0
2
1
Register Descriptions
1
1
1
PWMA
0
1
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