M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 161

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 13.1.1.1. Clock Synchronous Serial I/O Mode Specifications
6
0
NOTES:
13.1.1. Clock Synchronous serial I/O Mode
2
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Error detection
Select function
9
C
0 .
B
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1.1.1
lists the specifications of the clock synchronous serial I/O mode. Table 13.1.1.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
2 /
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register “0”
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
3. The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
0
0
2
6
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
unchanged.
0
A
F
2
e
0 -
G
b
1 .
2
o r
Item
0
, 5
u
0
p
2
0
(
M
0
7
1
6
C
page 142
2 /
6
, A
M
• Transfer data length: 8 bits
• The CKDIR bit in the UiMR(i=0 to 2) register is set to “0” (internal clock) : fj/ (2(n+1))
• The CKDIR bit is set to “1” (external clock
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_
_
_
• Before reception can start, the following requirements must be met
_
_
_
• For transmission, one of the following conditions can be selected
_
from the UiTB register to the UARTi transmit register (at start of transmission)
_
• For reception
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
• Switching serial data logic (UART2)
• Transfer clock output from multiple pins selection (UART1)
• Separate CTS/RTS pins (UART0)
• UART1 pin remapping selection
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
f o
1
The UART1 pin can be selected from the P6
fj = f
data from the UARTi transmit register
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
Reception is enabled immediately by reading the UiRB register
This function reverses the logic value of the transmit/receive data
The output pin can be selected in a program from two UART1 transfer clock pins that
The TE bit in the UiC1 register is set to "1" (transmission enabled)
The TI bit in the UiC1 register is set to "0" (data present in UiTB register)
If CTS function is selected, input on the CTSi pin is “L”
The RE bit in the UiC1 register is set to "1" (reception enabled)
The TE bit in the UiC1 register is set to "1" (transmission enabled)
The TI bit in the UiC1 register is set to "0" (data present in the UiTB register)
The UiIRS bit
The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
have been set
CTS
_________
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
6
_______
3
C
2
1SIO
2 /
9
0
6
and RTS
, B
, f
_______ _______
2SIO
M
_________
1
(2)
(3)
, f
6
0
C
8SIO
_______
is set to "0" (transmit buffer empty): when transferring data
are input/output from separate pins
2 /
6
, f
) T
32SIO
. n: Setting value of UiBRG register
_______
Specification
_______
7
) : Input from CLKi pin
to P6
_______ _______
4
or P7
3
to P7
0
.
00
(1)
16
(1)
to FF
13. Serial I/O
16