M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 236

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
16.4 Port Control Register
16.5 Pin Assignment Control register (PACR)
16.6 Digital Debounce function
e
E
1
. v
J
6
0
2
C
9
0 .
B
Figure 16.4.1 shows the port control register.
When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port
latch can be read no matter how the PD1 register is set.
Figure 16.5.1 shows the PACR. After reset set the PACR2 to PACR0 bit before you input and output it to
each pin. When the PACR register isn’t set up, the input and output function of some of the pins doesn’t
work.
PACR2 to PACR0 bits: control the pins enabled for use.
U1MAP: controls the assignment of UART1 pins.
PACR is write protected by PRC2 bit in the PRCR register. PRC2 bit must be set immediately before the
write to PACR.
Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction.
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively. Additionally, a digital debounce function is disabled to the port P1
input and port P8
Filter width :
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or
a rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 00
function. Setting to FF
2 /
0
0
6
2
0
A
F
2
e
G
0 -
b
At reset, these bits are “000”.
In 48-pin package, set these bits to “100
In 42-pin package, set these bits to “001
If the U1MAP bit is set to “0” (P6
P6
If the U1MAP bit is set to “1” (P7
P7
1 .
o r
2
0
, 5
u
5
1
0
/CLK
/CLK
p
2
0
(
M
0
7
1
1
1
, P6
, P7
6
5
C
page 217
input. Figure 16.6.1 shows the NDDR register and the P17DDR register.
2 /
(n+1)
6
2
6
/RxD
/RxD
16
, A
disables the digital filter. See Figure 16.6.2 for details.
M
1
1
1
f o
1/ f8 n: count value set in the NDDR register and P17DDr register
, and P6
, and P7
________
6
3
C
2
2 /
9
6
, B
7
3
/TxD
/TxD
M
7
3
1
6
to P6
to P7
C
1
1
.
.
2 /
6
_______ _____
4
0
) T
2
2
) the UART1 functions are mapped to P6
) the UART1 functions are mapped to P7
”.
”.
16
to FF
16
when using the digital debounce
16. Programmable I/O Ports
4
0
/CTS
/CTS
1
1
/RTS
/RTS
1
1
,
,
7