M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 194

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
NOTES:
Table 13.1.6.1. SIM Mode Specifications
6
0
13.1.6 Special Mode 4 (SIM Mode) (UART2)
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
(2)
Error detection
2
9
C
Interrupt request
generation timing
0 .
B
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmission com-
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Tables 13.1.6.1 lists the specifications of SIM mode. Table 13.1.6.2 lists the registers used in the SIM
mode and the register values set.
2 /
0
0
2
6
unchanged.
plete) and the U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be sure to clear
the IR bit to “0” (no interrupt request) after setting these bits.
0
A
F
2
e
0 -
G
b
1 .
2
o r
Item
0
, 5
u
0
p
2
0
(
M
0
7
1
6
C
page 175
2 /
6
, A
M
• Direct format
• Inverse format
• The CKDIR bit in the U2MR register is set to “0” (internal clock) : fi/(16(n+1))
• The CKDIR bit is set to “1” (external clock
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
• For transmission
• For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
1
fi = f
f
When the serial I/O finished sending data from the U2TB transfer register (the U2IRS bit
is set to "1")
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
This error occurs when the number of stop bits set is not detected
During reception, if a parity error is detected, parity error signal is output from the
TxD
During transmission, a parity error is detected by the level of input to the R
when a transmission interrupt occurs
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
f o
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
The RE bit in the U2C1 register is set to "1" (reception enabled)
Start bit detection
EXT
6
3
C
2
: Input from CLK
2
1SIO
2 /
9
pin.
6
, B
, f
2SIO
M
1
(1)
, f
6
C
8SIO
2 /
6
, f
2
) T
32SIO
pin.
. n: Setting value in U2BRG register
n: Setting value in U2BRG register
Specification
) : f
EXT
/(16(n+1))
00
00
16
16
to FF
to FF
13. Serial I/O
X
D
16
2
16
pin