M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 174

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 13.1.2.3.1. Transfer Format
0
6
2
9
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B
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0
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13.1.2.2. Counter Measure for Communication Error
13.1.2.3. LSB First/MSB First Select Function
2
6
0
If a communication error occurs while transmitting or receiving in UART mode, follow the procedure
below.
• Resetting the UiRB register (i=0 to 2)
• Resetting the UiTB register (i=0 to 2)
register
As shown in Figure 14.1.2.3.1, use the UFORM bit in the UiC0 register to select the transfer format.
This function is valid when transfer data is 8 bits long.
A
F
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
(1) Set the SMD2 to SMD0 bits in UiMR register “000
(2) Set the SMD2 to SMD0 bits in UiMR register “001
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiC1
(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)
(2) When the UFORM bit in the UiC0 register "1" (MSB first)
NOTE:
i = 0 to 2
2
CLK
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CLK
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X
X
X
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D
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1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0"
i
i
i
i
i
i
0
, 5
u
0
(transmit data output at the falling edge and the receive data taken in at the rising
edge of the transfer clock), the UiLCH bit in the UiC1 register is set to "0" (no
reverse), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE
bit in the UiMR register is set to "1" (parity enabled).
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page 155
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ST
ST
ST
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7
7
6
3
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2
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6
6
, B
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D
D
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2
2
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5
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D
D
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4
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D
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4
4
3
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5
5
2
” (Serial I/O disabled)
”, “101
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6
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2
”, “110
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7
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”
P
P
P
P
SP
SP
SP
SP
ST: Start bit
P: Parity bit
SP: Stop bit
13. Serial I/O