M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 187

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
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J
NOTES:
6
Table 13.1.4.1. Special Mode 2 Specifications
0
13.1.4 Special Mode 2 (UART2)
Transfer data format
Transfer clock
Transmit/receive control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
2
C
9
0 .
B
2 /
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 13.1.4.1 lists the specifications of Special Mode 2. Table 13.1.4.2 lists the registers
used in Special Mode 2 and the register values set. Figure 13.1.4.1 shows communication control ex-
ample for Special Mode 2.
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register “0”
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
0
0
6
2
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the U2C0 register “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
unchanged.
A
0
F
2
e
G
0 -
b
o r
1 .
2
Item
0
, 5
u
0
p
2
0
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M
0
7
1
6
C
page 168
2 /
6
, A
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• Transfer data length: 8 bits
• Master mode
• Slave mode
Controlled by input/output ports
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
_
• While transmitting, one of the following conditions can be selected
_
ferring data from the U2TB register to the UART2 transmit register (at start of transmission)
_
• While receiving
• Overrun error
• Clock phase setting
data from the UART2 transmit register
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
1
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f
The CKDIR bit is set to “1” (external clock selected) : Input from CLK2 pin
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 7th bit of the next data
Selectable from four combinations of transfer clock polarities and phases
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
The RE bit in the U2C1 register is set to "1" (reception enabled)
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in the U2TB register)
The U2IRS bit in the U2C1 register is set to "0" (transmit buffer empty): when trans-
The U2IRS bit is set to "1" (transfer completed): when the serial I/O finished sending
f o
6
C
3
2
1SIO
2 /
9
6
, B
, f
2SIO
M
1
(2)
6
, f
C
8SIO
2 /
6
, f
) T
32SIO
. n: Setting value of U2BRG register
Specification
00
(1)
16
(1)
to FF
13. Serial I/O
16