M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 329

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
0
C
2
9
0 .
B
2 /
0
0
19.7.1.4 Timer A (Pulse Width Modulation Mode)
6
2
A
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
4. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
0
F
2
e
G
0 -
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
• Stop counting.
• When TAi
• When TAi
(three-phase output forcible cutoff by input on SD pin enabled), the TA1
pins go to a high-impedance state.
b
o r
1 .
2
0
u
, 5
0
p
2
(
0
M
0
7
1
6
C
OUT
OUT
page 310
2 /
6
pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
pin is output “L”, both output level and the IR bit remains unchanged.
, A
M
1
f o
6
C
3
2
2 /
9
6
, B
M
1
6
C
_____
2 /
6
) T
_____
OUT
, TA2
OUT
19. Usage Notes
and TA4
OUT