M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 76

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
7.7 System Clock Protective Function
7.8 Oscillation Stop and Re-oscillation Detect Function
. v
J
1
Table 7.8.1. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
0
6
Oscillation stop detectable clock and
frequency bandwidth
Enabling condition for oscillation stop,
re-oscillation detection function
Operation at oscillation stop,
re-oscillation detection
2
9
When the main clock is selected for the CPU clock source, this function protects the clock from modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit in the PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit in the CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for
the CPU clock source):
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit in the PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is set to “1”.
The oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and
reoscillation. At oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection
interrupt are generated. Depending on the CM27 bit in the CM2 register. The oscillation stop detection
function can be enabled and disabled by the CM20 bit in the CM2 register. Table 7.8.1 lists a specification
overview of the oscillation stop and re-oscillation detect function.
C
0 .
B
2 /
0
0
2
6
0
F
A
2
e
0 -
b
G
1 .
2
o r
0
, 5
0
u
Item
2
p
0
(
0
M
7
1
6
C
page 57
2 /
6
, A
M
f o
1
6
3
C
2
2 /
9
6
, B
M
•Reset occurs (when the CM27 bit is set to "0")
•Oscillation stop, re-oscillation detection interrupt occurs(when the CM27 bit is
f(X
Set the CM20 bit to “1”(enable)
set to "1")
1
6
IN
C
)
2 /
6
2 MHz
) T
Specification
7. Clock Generation Circuit