M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 177

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
NOTES:
Table 13.1.3.1. I
0
13.1.3 Special Mode 1 (I
C
Interrupt request
generation timing
2
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Error detection
Select function
9
0 .
B
2 /
I
the specifications of the I
mode and the register values set. Table 13.1.3.4 lists the I
the block diagram for I
As shown in Table 13.1.3.2, the microcomputer is placed in I
bits to ‘010
output does not change state until SCL
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
2
0
0
C bus mode is provided for use as a simplified I
6
unchanged.
2
A
0
F
2
e
G
0 -
b
1 .
o r
2
Item
0
, 5
u
0
p
2
2
(
0
’ and the IICM bit to “1”. Because SDA
M
0
7
2
1
C bus Mode Specifications
6
C
page 158
2 /
6
, A
2
C bus mode. Figure 13.1.3.2 shows SCL
2
M
C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I
• Transfer data length: 8 bits
• During master
• Before transmission can start, the following requirements must be met
_
_
• Before reception can start, the following requirements must be met
_
_
_
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error
• Arbitration lost
• SDA2 digital delay
• Clock phase setting
1
f o
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f
• During slave
The CKDIR bit is set to “1” (external clock) : Input from SCL
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
Timing at which the ABT bit in the U2RB register is updated can be selected
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
With or without clock delay selectable
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
The RE bit in the U2C1 register is set to "1" (reception enabled)
The TE bit in the U2C1 register is set to "1" (transmission enabled)
The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)
6
2
C
3
C bus mode)(UART2)
2
2 /
1SIO
9
6
, B
, f
2SIO
M
1
2
(2)
6
, f
goes low and remains stably low.
C
8SIO
2 /
6
, f
) T
32SIO
2
C bus interface compatible mode. Table 13.1.3.1 lists
2
. n: Setting value in the U2BRG register
transmit output has a delay circuit attached, SDA
2
C bus mode fuctions. Figure 13.1.3.1 shows
2
C bus mode by setting the SMD2 to SMD0
Specification
2
timing.
2
pin
(1)
00
(1)
16
13. Serial I/O
to FF
2
C bus
16