M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 60

• Manufacturer Part Number: M30260F6AGP#U3
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
. v
J
1
Figure 7.3. CM1 Register
Figure 7.4. ROCR Register
0
6
2
9
C
0 .
B
2 /
b7
System clock control register 1 (1)
0
0
NOTES:
NOTE:
2
On-chip Oscillator Control Register
6
0
b6
F
b7
A
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
4. If the CM10 bit is “1” (stop mode), X
5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit
6. When the PM21 bit in the PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.
7. Effective when CM07 bit is “0” and CM21 bit is “0” .
2
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).
e
0 -
speed mode, the CM15 bit is set to “1” (drive capability high).
are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register is set
to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
to “1” (PLL clock).
When the PM22 bit in the PM2 register is set to “1” (watchdog timer count source is on-chip oscillator clock), writing to the CM10
bit has no effect.
b5
b
G
0
b6
1 .
2
o r
b4
0
0 0
, 5
0 0
b5
0
u
b3
2
p
0
b4
(
0
b2
0
M
7
b3
1
b1
6
C
b0
b2
page 41
2 /
b1
6
Bit symbol
, A
(b4-b2)
CM15
CM16
CM17
CM10
CM11
b0
Symbol
CM1
M
f o
1
Bit Symbol
6
ROCR0
ROCR1
ROCR2
ROCR3
3
C
(b6-b4)
2
OUT
(b7)
All clock stop control bit
(4, 6)
System clock select bit 1
(6, 7)
X
select bit (2)
Main clock division
select bits (3)
2 /
Reserved bit
9
Symbol
ROCR
IN
6
-X
goes “H” and the internal feedback resistor is disconnected. The X
, B
OUT
M
Bit name
drive capacity
Frequency select bits
Divider select bits
1
Nothing is assigned. When write, set to 0. When read, its
content is undefined
Reserved bit
6
Address
0007
C
(1)
2 /
Bit Name
16
6
) T
Address
After reset
00100000
025C
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
1 : PLL clock (5)
Must set to
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
0 : LOW
1 : HIGH
16
2
“0”
b1 b0
0 0: f
0 1: f
1 0: Do not set to this value
1 1: f
0 0: Do not set to this value
0 1: divide by 2
1 0: divide by 4
1 1: divide by 8
Set to 0
b3 b2
After Reset
X0000101
1
2
3
(ROC)
(ROC)
(ROC)
Function
Function
2
7. Clock Generation Circuit
CIN
and X
COUT
pins
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW