XR17D152CM-F Exar Corporation, XR17D152CM-F Datasheet
XR17D152CM-F
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XR17D152CM-F Summary of contents
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JUNE 2004 GENERAL DESCRIPTION 1 The XR17D152 (D152 monolithic dual PCI Bus Universal Asynchronous Receiver and Transmitter (UART) in Exar’s PCI Bus UART family. The device is designed to meet today’s 32-bit PCI Bus and high bandwidth requirement ...
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... AD27 94 AD26 95 AD25 96 AD24 97 C/BE3# 98 IDSEL 99 VIO 100 ORDERING INFORMATION ART UMBER ACKAGE XR17D152CM 100-Lead TQFP XR17D152IM 100-Lead TQFP XR17D152 100-TQFP (14x14x1.0mm PERATING EMPERATURE 0°C to +70°C -40°C to +85°C 2 áç áç áç áç REV. 1.2.0 MPIO2 50 ...
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REV. 1.2.0 PIN DESCRIPTIONS AME IN YPE PCI LOCAL BUS INTERFACE RST# 86 CLK 87 AD31-AD24, 90-97, I/O AD23-AD16, 2-9, AD15-AD8, 24-31, AD7-AD0 35-42 FRAME# 13 C/BE3#- 98, 12, C/BE0# 21, 34 ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART PIN DESCRIPTIONS AME IN DSR0# 68 CD0# 69 RI0# 70 TX1 62 RX1 55 RTS1# 60 CTS1# 56 DTR1# 61 DSR1# 57 CD1# 58 RI1# 59 ANCILLARY ...
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REV. 1.2.0 PIN DESCRIPTIONS AME IN YPE TMRCK 75 ENIR 74 EN485# 65 TEST# 79 VCC 54, 80 PWR VIO 10, 22, 32, 43, PWR 89, 100 GND 1, 11, 23, 33, ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART FUNCTIONAL DESCRIPTION The XR17D152 integrates the functions of 2 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, ...
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REV. 1.2.0 1.0 APPLICATION EXAMPLES The XR17D152 is designed to operate with VCC (voltage to the UART Core Logic) greater than or equal to VIO. For a universal add-in card usually unknown whether it ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART IGURE YPICAL PPLICATIONS IN AN Example 1 VIO = 3.3V, VCC = 5V Example 2 VIO = 5V, VCC = 5V Example 3 VIO = 3.3V, VCC ...
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REV. 1.2.0 2.0 XR17D152 REGISTERS The XR17D152 UART has three different sets of registers as shown in configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration feature makes ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS The PCI local bus configuration space registers are responsible for setting up the device’s operating environment in the PCI local bus. The pre-defined operating ...
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REV. 1.2 PCI L ABLE DDRESS ITS YPE 0x18h 31:0 RO Unimplemented Base Address Register (returns zeros) 0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x20 31:0 RO Unimplemented Base ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART T 2: XR17D152 D ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 ...
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REV. 1.2 ABLE EVICE A DDRESS R EGISTER [A7:A0] Ox08A RESET Ox08B SLEEP Ox08C DREV Ox08D DVID Ox08E REGB Ox08F MPIOINT Ox090 MPIOLVL Ox091 MPIO3T Ox092 MPIOINV Ox093 MPIOSEL ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 2.2.1 The Interrupt Status Register The XR17D152 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme uses bits ...
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REV. 1.2 IGURE HE LOBAL NTERRUPT INT3 Register Rsvd Rsvd Rsvd Bit Bit Bit Bit Bit Bit Bit Bit N+2 N+1 N N+2 N+1 N N+2 N UART ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 2.2.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL XX-XX-00-00 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal ...
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REV. 1.2.0 TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 2.2.6 SLEEP [31:24] - (default 0x00) The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power consumption when the system needs to put the UART(s) ...
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REV. 1.2.0 2.2.7 Device Identification and Revision There are two internal registers that provide device identification and revision, DVID and DREV registers. The 8-bit content in the DVID register provides device identification. A return value of ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) MPIOSEL ...
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REV. 1.2.0 MPIOLVL [7:0] (default 0x00) Output pin level control and input level status. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 3.0 CRYSTAL OSCILLATOR / BUFFER The D152 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the ...
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REV. 1.2.0 4.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART Channel ReceiveData in 32-bit alignment through the Configuration Register Address Receive Data Byte n ...
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REV. 1.2.0 Channel Transmit Data in 32-bit alignment through the Configuration Register Address Transmit Data Byte n+3 Transmit Data Byte n ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART F 11 IGURE AUD ATE Crystal XTAL1 Osc/ XTAL2 Buffer Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the operating data rate. Table ...
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REV. 1.2.0 5.2 Transmitter The transmitter section comprises of 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8- bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART F 13 IGURE RANSMIITTER PERATION nsm low tro cte rs ...
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REV. 1.2.0 5.3.2 Receiver Operation in non-FIFO Mode F 14 IGURE ECEIVER PERATION IN NON ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 5.4 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. ...
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REV. 1.2.0 F 16. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 5.5 Infrared Mode Each UART in the D152 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates both UART ...
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REV. 1.2.0 5.6 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with the EXAR enhanced feature registers located on next 8 addresses locations. ...
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REV. 1.2.0 T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE XCHAR ...
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REV. 1.2.0 IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART Interrupt Generation: • LSR is by any of the LSR bits and 4. • RXRDY trigger level. • RXRDY Time-out is by the a 4-char ...
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REV. 1.2.0 ISR[4]: Xoff/Xon or Special Character Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the ...
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REV. 1.2.0 5.8.7 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output ...
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REV. 1.2.0 MCR[5]: Xon-Any Enable Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default). Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data transmission. MCR[6]: Infrared ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In ...
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REV. 1.2.0 MSR[5]: DSR Input Status This input may be used for auto DTR/DSR flow control function, see CTS or DTR/DSR) Flow Control Operation” on page 30 is not used, this bit is the compliment of ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 5.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode ...
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REV. 1.2 ABLE ELECTABLE FCTR B -3 FCTR ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. ...
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REV. 1.2.0 EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/DTR is selected, an interrupt will be generated ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-1:0] RTS#[ch-1:0] DTR#[ch-1:0] EECK EECS ...
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REV. 1.2.0 6.0 PROGRAMMING EXAMPLES 6 NLOADING ECEIVE ATA It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any UART channel (address ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART ABSOLUTE MAXIMUM RATINGS Power Supply Range (VCC) Voltage at any PCI Bus Pin Voltage at any non-PCI Bus Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.0mm 144-TQFP) ELECTRICAL CHARACTERISTICS ...
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REV. 1.2.0 AC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5-5.5V TA (-40 to +85 C for industrial grade package YMBOL ARAMETER ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V TA (-40 to +85 C for industrial grade ...
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REV. 1.2.0 AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V TA (-40 to +85 C for industrial grade package YMBOL ARAMETER ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART F 19 IGURE IMING OR XTERNAL 2V External Clock 0.8V I XTAL1 P LOCK NPUT ECLK T ECH 56 áç áç áç áç REV. ...
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REV. 1.2.0 F 20. PCI B C IGURE US ONFIGURATION ost ost A D[31:0] H ost /BE [3:0]# H ost ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART F 21 IGURE EVICE ONFIGURATION AND CLK Host FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host TRDY# Target ...
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REV. 1.2 IGURE EVICE ONFIGURATION REGISTERS TION CLK FRAM ata AD[31: ress ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART F 23 IGURE EVICE ONFIGURATION CLK H ost 1 FRAM E# H ost AD[31: ost Target Bus C/BE[3:0]# Byte Ena ble ...
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REV. 1.2.0 F 24. 5V PCI B C IGURE US LOCK 4 nSec (max) CLK Tval (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Bused Signal Input UNIVERSAL (3.3V AND 5V) PCI ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART F 25. 3.3V PCI B C IGURE US LOCK 1.44 ns (max) CLK Tvalid (2-11 ns) Bused Signal Output Delay Ton (2 ns min) Tri-State Output Bused Signal Input 11 ns ...
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REV. 1.2 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 27 IGURE ECEIVE ATA EADY START BIT RX Data ...
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XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART PACKAGE DIMENSIONS 100 LEAD T HIN QUAD FLAT PACK Seating Plane YMBOL ...
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... June 2004 Rev 1.2.0 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR17D152 REV. 1.2.0 GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES ............................................................................................................................................................. 1 IGURE LOCK IAGRAM XR17D152 ........................................................................................................................................... 2 IGURE THE .................................................................................................................................2 ORDERING INFORMATION P D .........................................................................................................................................3 IN ...
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UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART 5.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 27 5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ IGURE RANSMITTER PERATION IN NON 5.3 RECEIVER ...................................................................................................................................................... 28 5.3.1 ...
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XR17D152 REV. 1.2 IGURE EVICE ONFIGURATION F 24. 5V PCI B C .................................................................................................................................................... 61 IGURE US LOCK F 25. 3.3V PCI B C ................................................................................................................................................. 62 IGURE US LOCK F 26 IGURE RANSMIT ATA ...