XR17D152CM-F Exar Corporation, XR17D152CM-F Datasheet - Page 24

• Manufacturer Part Number: XR17D152CM-F
• Description: IC UART PCI BUS DUAL 100TQFP
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 422 or RS- 485r

Specifications of XR17D152CM-F

• Number Of Channels: 2, DUART
• Package / Case: 100-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.25 V or 5.5 V
• Supply Voltage (min): 4.5 V or 4.75 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1288

XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
The XR17D152 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0) and 0x380 (channel 1). The entire RX data along with the status can be
downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be
read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly.
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0) and 0x300 (channel 1).
4.1.2
4.1.3
Data Bit-31
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
Write n+0 to n+3
Write n+4 to n+7
PCI Bus
R
W
PCI Bus
EAD
B7 B6 B5 B4 B3 B2 B1 B0
RITE
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Etc.
RX FIFO,
Etc
Receive Data Byte n+3
TX FIFO
Special Rx FIFO Data Unloading at locations 0x180 (channel 0) and 0x380 (channel 1)
Tx FIFO Data Loading at locations 0x100 (channel 0) and 0x300 (channel 1)
E
RRORS
Channel 0 to 1 ReceiveData in 32-bit alignment through the Configuration Register Address
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
FIFO Data n+1
FIFO Data n+3
FIFO Data n+3
FIFO Data n+7
B
B
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+1
3
3
Receive Data Byte n+2
the Configuration Register Address 0x0180 and 0x0380
FIFO Data n+2
FIFO Data n+6
0x0100 and 0x0300
LSR n+1
LSR n+3
B
B
YTE
YTE
24
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+0
Receive Data Byte n+1
FIFO Data n+0
FIFO Data n+2
FIFO Data n+1
FIFO Data n+5
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
Receive Data Byte n+0
áç
áç
áç
áç
FIFO Data n+0
FIFO Data n+4
LSR n+0
LSR n+2
B
B
YTE
YTE
REV. 1.2.0
Data Bit-0
Data Bit-0
0
0
PCI Bus
PCI Bus