XR17D152CM-F Exar Corporation, XR17D152CM-F Datasheet - Page 44

• Manufacturer Part Number: XR17D152CM-F
• Description: IC UART PCI BUS DUAL 100TQFP
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 422 or RS- 485r

Specifications of XR17D152CM-F

• Number Of Channels: 2, DUART
• Package / Case: 100-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.25 V or 5.5 V
• Supply Voltage (min): 4.5 V or 4.75 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1288

XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty; it is cleared when at least 1 byte is written to the transmit FIFO.
LSR[6]: Transmit Shift Register Empty Flag
This bit is the Transmit Shift Register Empty indicator. This bit is set to a logic 1 whenever the transmitter goes
idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is
set to one whenever the transmit FIFO and transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose
inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
MSR[1]: Delta DSR# Input Flag
MSR[2]: Delta RI# Input Flag
MSR[3]: Delta CD# Input Flag
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7) and RTS/CTS flow control select (MCR bit-2). Auto CTS flow control allows starting and
stopping of local data transmissions based on the modem CTS# signal. A logic 1 on the CTS# pin will stop
UART transmitter as soon as the current character has finished transmission, and a logic 0 will resume data
transmission. If automatic hardware flow control is not used, MSR bit-4 bit is the compliment of the CTS# input.
However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may
be used as a general purpose input when the modem interface is not used.
5.8.10
Logic 0 = No FIFO error (default).
Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3.
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Modem Status Register (MSR) - Read-Only
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REV. 1.2.0