XR17D152CM-F Exar Corporation, XR17D152CM-F Datasheet - Page 51

• Manufacturer Part Number: XR17D152CM-F
• Description: IC UART PCI BUS DUAL 100TQFP
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 422 or RS- 485r

Specifications of XR17D152CM-F

• Number Of Channels: 2, DUART
• Package / Case: 100-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.25 V or 5.5 V
• Supply Voltage (min): 4.5 V or 4.75 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1288

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REV. 1.2.0
It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any
UART channel (address 0x180 for channel 0), do a dummy read to the Device ID (DVID) register in the Config-
uration Register of the device. The Special Receive FIFO Data with Status register can then be read multiple
times subsequently without any byte-swapping problem as long as no other register (except the Device ID reg-
ister) is accessed in between data unload. If you must read or write to another register, make that dummy read
to the DVID register again and continue with data unloading.
A step by step procedure describing the sequence for a target channel is shown below. From the receive data
service routine:
NOTE: If you must do other Read/Write operations to other register(s) during data unloading, repeat steps 1 &
2 to continue unloading data plus status from the ‘Special Receive FIFO Data with Status’ register of the target
channel.
Some Examples of using the Special Receive FIFO Data with Status:
E
E
E
* In case some other registers need to be accessed in between ‘Special Receive FIFO Data with Status’
reads, a ‘Read DVID’ instruction has to be inserted before resuming ‘Special Receive FIFO Data with Status’
read operation.
6.0 PROGRAMMING EXAMPLES
6.1
•
•
XAMPLE
XAMPLE
XAMPLE
Do a dummy read to Device ID (DVID) register. Address 0x8D in BYTE alignment or address 0x8C in
DWORD alignment.
Read the data byte and its associated error status from ‘Special Receive FIFO Data with Status’ register of
the target channel until done or empty when one of the LSR status byte bit-0=0.
.....................
Read LSR
Read DVID
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)*
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)
....................
.....................
Read Global Interrupt Register INT0 (address 0x080)
Read INT1 through INT3 registers to identify interrupting channel (address 0x081 through 0x083)
Read DVID
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)*
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)
................
................
Read Global Interrupt Register INT0 (address 0x080)
Read ISR register of interrupting channel
Read DVID
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)*
Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)
................
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51
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UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
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XR17D152
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ET