XR17D152CM-F Exar Corporation, XR17D152CM-F Datasheet - Page 36

• Manufacturer Part Number: XR17D152CM-F
• Description: IC UART PCI BUS DUAL 100TQFP
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 422 or RS- 485r

Specifications of XR17D152CM-F

• Number Of Channels: 2, DUART
• Package / Case: 100-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.25 V or 5.5 V
• Supply Voltage (min): 4.5 V or 4.75 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1288

XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
N
See
See
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and
receiver. The baud rate is programmed through registers DLL and DLM which are only accessible when LCR
bit-7 is set to logic 1. See
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and
also encoded in INT (INT0-INT3) register in the Device Configuration Registers.
IER
When the receive FIFO (FCR bit-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the
RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
IER
When FCR BIT-0 equals a logic 1 for FIFO enable, resetting IER bits 0-3 enables the 158 in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BITS 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
5.8
T
5.8.1
5.8.2
5.8.3
5.8.4
OTE
A
ABLE
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
A3-A0
DDRESS
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
VERSUS
VERSUS
“Section 5.3, Receiver” on page 28
“Section 5.2, Transmitter” on page 27
: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17D152. They are present for 16C550
compatibility during Internal loopback, see
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
Registers
Receive Holding Register (RHR) - Read-Only
Transmit Holding Register (THR) - Write-Only
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
Interrupt Enable Register (IER) - Read/Write
XCHAR
XOFF1
XOFF2
XON1
XON2
N
R
R
R
AME
EG
ECEIVE
ECEIVE
W
R
/T
EAD
FIFO I
RITE
W
W
W
W
R
RANSMIT
/
“Section 5.1, Programmable Baud Rate Generator” on page 25
NTERRUPT
B
Bit-7
Bit-7
Bit-7
Bit-7
IT
-7
FIFO P
B
Bit-6
Bit-6
Bit-6
Bit-6
M
OLLED
IT
ODE
for complete details.
-6
for complete details.
O
M
Figure 18
PERATION
B
ODE
Bit-5
Bit-5
Bit-5
Bit-5
IT
-5
O
PERATION
36
.
B
Bit-4
Bit-4
Bit-4
Bit-4
IT
-4
B
Bit-3
Bit-3
Bit-3
Bit-3
IT
-3
B
Bit-2
Bit-2
Bit-2
Bit-2
IT
-2
S
HADED BITS ARE ENABLED BY
Xon Det.
Indicator
B
Bit-1
Bit-1
Bit-1
Bit-1
IT
-1
for more detail.
áç
áç
áç
áç
Xoff Det.
Indicator
B
Bit-0
Bit-0
Bit-0
Bit-0
IT
-0
REV. 1.2.0
EFR B
C
after read
Self-clear
OMMENT
IT
-4.