XR17D152CM-F Exar Corporation, XR17D152CM-F Datasheet - Page 15

• Manufacturer Part Number: XR17D152CM-F
• Description: IC UART PCI BUS DUAL 100TQFP
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 422 or RS- 485r

Specifications of XR17D152CM-F

• Number Of Channels: 2, DUART
• Package / Case: 100-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.25 V or 5.5 V
• Supply Voltage (min): 4.5 V or 4.75 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1288

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REV. 1.2.0
.
F
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
P
IGURE
RIORITY
N+2
Bit
1
2
3
4
5
6
7
x
Rsvd
6. T
N+1
Bit
B
HE
Bit
N
IT
[
0
0
0
0
1
1
1
1
N
G
INT3 Register
+2]
N+2
Bit
LOBAL
Rsvd
N+1
Bit
B
IT
I
T
[
NTERRUPT
Bit
0
0
1
1
0
0
1
1
N
N
ABLE
+1]
T
N+2
Bit
ABLE
5: UART C
Rsvd
N+1
B
Bit
IT
0
1
0
1
0
1
0
1
R
6: UART C
[
N
EGISTER
Bit
N
]
N+2
None
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only in channel 0, reserved in channel 1.
TIMER Time-out. Available only in channel 0, reserved channel 1.
Bit
HANNEL
Rsvd
, INT0, INT1, INT2
INT0, INT1, INT2 and INT3
N+1
Bit
HANNEL
Interrupt Registers,
INT2 Register
Bit
N
[1:0] I
N+2
Bit
15
[1:0] I
NTERRUPT
Rsvd
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
N+1
Bit
NTERRUPT
Bit
N
AND
N+2
I
Bit
NTERRUPT
S
INT3
OURCE
Rsvd
Rsvd
N+1
Bit-7
Bit
C
LEARING
Rsvd Rsvd
Bit-6
Bit
N
E
S
NCODING
OURCE
Bit-5
N+2
Bit
Channel-1
:
INT0 Register
Rsvd
Bit-4
N+1
INT1 Register
Bit
(
S
)
Rsvd Rsvd Ch-1 Ch-0
Bit-3
Bit
N
N+2
Bit-2
Bit
Channel-0
N+1
Bit-1
Bit
XR17D152
Bit-0
Bit
N