IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 103
![KIT DEVELOPMENT I.MX257, ARM926](/photos/37/58/375862/imx25kbsbd_sml.jpg)
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 103 of 154
- Download datasheet (2Mb)
3.7.16
Figure 76
Table 80
Freescale Semiconductor
describe the timing parameters shown in the respective figures.
LCD_CLK (LCD_DATA[6])
and
LCD_CLK (LCD_DATA[6])
LCD_CLK (LCD_DATA[6])
LCD_CLK (LCD_DATA[6])
Smart Liquid Crystal Display Controller (SLCDC)
SDATA (LCD_DATA[7])
SDATA (LCD_DATA[7])
SDATA (LCD_DATA[7])
SDATA (LCD_DATA[7])
Figure 77
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device
LCD_CS
LCD_CS
LCD_CS
LCD_CS
show SLCDC timing for serial and parallel transfers respectively.
RS
RS
RS
RS
tcss
tcss
tcss
(This diagram shows the case SCKPOL = 1, CSPOL = 0)
tcss
(This diagram shows the case SCKPOL = 0, CSPOL = 0)
(This diagram shows the case SCKPOL = 0, CSPOL = 1)
(This diagram shows the case SCKPOL = 1, CSPOL = 1)
MSB
MSB
MSB
MSB
RS=0 => command data, RS=1=> display data
RS=0 => command data, RS=1=> display data
RS=0 => command data, RS=1=> display data
RS=0 => command data, RS=1=> display data
tcyc
tcyc
tcyc
tcyc
tds
tds
tds
tds
trss
trss
trss
trss
tcl
tcl
tcl
tcl
tch
tdh
tch
tdh
tch
tdh
tch
tdh
tcsh
tcsh
tcsh
tcsh
LSB
LSB
LSB
LSB
trsh
trsh
trsh
trsh
Table 79
and
103
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