IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 114
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 114 of 154
- Download datasheet (2Mb)
Figure 83
shows the timing for ADC normal operation.
Figure 83. Timing for ADC Normal Operation
When the ADC is used so that the idle clock cycles occur between conversions (due to the negation of soc),
the selin inputs must be stable at least 1 clock cycle before the clock's rising edge where the soc signal is
latched. Also, selrefp and selrefn must be stable by the time the soc signal is latched. These conditions are
met if enadc=1 and reset=0 throughout ADC operation, including the idle cycles. If the conditions are not
met, or if power is lost during ADC operation, then a new start-up sequence is required for ADC to become
operational again.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
114
Freescale Semiconductor
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