CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 28

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Table 38. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]
Table 39. Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
This register is used to trim the Internal 24 MHz Oscillator using received low speed USB packets as a timing reference. The
USB Osclock circuit is active when the Internal 24 MHz Oscillator provides the USB clock
Bits 7:2
Bit 1
Bit 0
Bit #
Field
Read/Write
Default
Bits 7:6
Bits 5:4
Note The 1024-μs interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency causes
a corresponding change in the 1024 μs interval timer frequency
Bits 3:2
Bits 1:0
Reserved
Fine Tune Only
0 = Enable
1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be
allowed to perform a course tuning to tune the oscillator for correct USB SIE operation. After the oscillator is prop-
erly tuned this bit can be set to reduce variance in the internal oscillator frequency that would be caused by course
tuning
USB Osclock Disable
0 = Enable. With the presence of USB traffic, the Internal 24 MHz Oscillator precisely tunes to 24 MHz ± 1.5%
1 = Disable. The Internal 24 MHz Oscillator is not trimmed based on USB packets. This setting is useful when the
internal oscillator is not sourcing the USBSIE clock
TCAPCLK Divider
TCAPCLK Divider controls the TCAPCLK divisor
00 = Divide by 2
01 = Divide by 4
10 = Divide by 6
11 = Divide by 8
TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK
0 0 = Internal 24 MHz Oscillator
0 1 = External crystal oscillator—external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is
enabled, CLKIN input if the external crystal oscillator is disabled (the XOSC Enable bit of the CLKIOCR Register is
cleared—Table
1 0 = Internal 32 kHz Low power Oscillator. However this configuration is not used in sleep mode.
1 1 = TCAPCLK Disabled
ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor.
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
ITMRCLK Select
0 0 = Internal 24 MHz Oscillator
0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is
enabled, CLKIN input if the external crystal oscillator is disabled
1 0 = Internal 32 kHz Low pow
1 1 = TCAPCLK
R/W
7
–
0
TCAPCL Divider
7
-
40)
R/W
6
–
0
6
-
er Oscillator. However this configuration is not used in sleep mode.
R/W
5
–
0
TCAPCLK Select
5
-
Reserved
4
–
0
R/W
4
-
3
–
0
R/W
ITMRCLK Divider
3
1
2
–
0
R/W
2
1
Fine Tune
Only
R/W
1
0
R/W
ITMRCLK Select
1
0
CYRF69213
USB Osclock
Disable
Page 28 of 77
R/W
0
0
R/W
0
0
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