CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 6

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Functional Block Overview
All the blocks that make up the PRoC LP are presented here.
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 3. Internal PA Output Power Step Table
Frequency Synthesizer
Before transmission or reception may commence, it is necessary
for the frequency synthesizer to settle. The settling time varies
depending on channel; 25 fast channels are provided with a
maximum settling time of 100 μ s.
The ‘fast channels’ (<100 μ s settling time) are every third
frequency, starting at 2400 MHz up to and including 2472 MHz
(for example, 0,3,6,9…….69 & 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16 gener-
ation and checking, and EOP detection and length field.
Data Rates and Data Transmission Modes
The SoC supports four different data transmission modes:
■
■
■
■
Both 64-chip and 32-chip DATA_CODE_ADR codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
Document #: 001-07552 Rev. *D
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR
derived code symbol transmitted.
In DDR mode, 2-bits are encoded in each DATA_CODE_ADR
derived code symbol transmitted. (As in the CYWUSB6934
DDR mode).
In SDR mode, 1 bit is encoded in each DATA_CODE_ADR
derived code symbol transmitted. (As in the CYWUSB6934
standard modes.)
PA Setting
7
6
5
4
3
2
1
0
Typical Output Power (dBm)
–10
–15
–20
–25
–30
+4
–5
0
sent in the same mode. In general, lower data rates reduces
packet error rate in any given environment.
By combining the DATA_CODE_ADR code lengths and data
transmission modes described above, the CYRF69213 IC
supports the following data rates:
■
■
■
■
■
■
Lower data rates typically provide longer range and/or a more
robust link.
Link Layer Modes
The CYRF69213 IC device supports the following data packet
framing features:
SOP – Packets begin with a 2-symbol Start of Packet (SOP)
marker. This is required in GFSK and 8DR modes, but is optional
in DDR mode and is not supported in SDR mode; if framing is
disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for
the SOP is different from that used for the ‘body’ of the packet,
and if desired may be a different length. SOP must be configured
to be the same length on both sides of the link.
EOP – There are two options for detecting the end of a packet.
If SOP is enabled, then a packet length field may be enabled.
GFSK and 8DR must enable the length field. This is the first
8 bits after the SOP symbol, and is transmitted at the payload
data rate. If the length field is enabled, an End of Packet (EOP)
condition is inferred after reception of the number of bytes
defined in the length field, plus two bytes for the CRC16 (if
enabled—see below). The alternative to using the length field is
to infer an EOP condition from a configurable number of
successive non correlations; this option is not available in GFSK
mode and is only recommended when using SDR mode.
CRC16 – The device may be configured to append a 16-bit
CRC16 to each packet. The CRC16 uses the USB CRC
polynomial with the added programmability of the seed. If
enabled, the receiver verifies the calculated CRC16 for the
payload data against the received value in the CRC16 field. The
starting value for the CRC16 calculation is configurable, and the
CRC16 transmitted may be calculated using either the loaded
seed value or a zero seed; the received data CRC16 is checked
against both the configured and zero CRC16 seeds.
CRC16 detects the following errors:
■
■
■
■
Figure 2
and lengths fields enabled.
1000 kbps (GFSK)
250 kbps (32-chip 8DR)
125 kbps (64-chip 8DR)
62.5 kbps (32-chip DDR)
31.25 kbps (64-chip DDR)
15.625 kbps (64-chip SDR)
Any one bit in error
Any two bits in error (irrespective of how far apart, which col-
umn, and so on)
Any odd number of bits in error (irrespective of the location)
An error burst as wide as the checksum itself
on page 7 shows an example packet with SOP, CRC16
CYRF69213
Page 6 of 77
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