CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 5

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

DDR MODE
Table 1. DDR Mode
SDR MODE
Table 2. SDR Mode
Document #: 001-07552 Rev. *D
TX_CFG_ADR
RX_CFG_ADR
XACT_CFG_ADR
FRAMING_CFG_AD
R
TX_OVERRIDE_AD
R
RX_OVERRIDE_AD
R
ANALOG_CTRL_AD
R
DATA32_THOLD_AD
R
EOP_CTRL_ADR
PREAMBLE_ADR
TX_CFG_ADR
RX_CFG_ADR
XACT_CFG_ADR
FRAMING_CFG_AD
R
TX_OVERRIDE_AD
R
RX_OVERRIDE_AD
R
ANALOG_CTRL_AD
R
DATA64_THOLD_AD
R
EOP_CTRL_ADR
PREAMBLE_ADR
REGISTER
REGISTER
0X16
0X4B
0X05
0X00
0X04
0X14
0X01
0X03
0x01
0xAAAA05
0X3E
0X4B
0X05
0X00
0X04
0X14
0X01
0X07
0xA1
0xAAAA09
VALUE
VALUE
64 chip PN code, SDR mode, PA = 6.
AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device
uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled
and RX buffer is configured to receive eight bytes maximum. Enables RXOW to allow new
packets to be loaded into the receive buffer. This also enables the VALID bit which is used by
the first generation radio’s error correction firmware.
AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to
Idle mode after Receive or Transmit. ACK timeout is set to 128 µs.
All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.
Disable Transmit CRC-16.
The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and the
receiver accepts bad packets that do not match the seed in the CRC_seed registers. Basically
this helps in communication with the first generation radio that does not have CRC capabilities.
Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow
channels in the first generation radio, for manual ACK consistency
Sets the number of allowed corrupted bits to 7 which is close to the recommended 12% value.
Sets the number of consecutive symbols for non correlation to detect end of packet.
register file. The number of preamble bytes to be sent should be >8.
32 chip PN Code, DDR, PA = 6
AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device
uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled
and the RX buffer is configured to receive eight bytes maximum.
AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to
Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs.
All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.
Disable Transmit CRC-16.
The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the
receiver accepts bad packets that do not match the seed in CRC_seed registers. Basically
this helps in communication with the first generation radio that does not have CRC capabilities.
Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow
channels in the first generation radio.
Sets the number of allowed corrupted bits to 3.
Sets the number of consecutive symbols for non correlation to detect end of packet.
file. The number of preamble bytes to be sent should be >4.
AAAA are the two preamble bytes. Any other byte can also be written into the preamble
AAAA are the two preamble bytes.Other Bytes can also be written into the preamble register
DESCRIPTION
DESCRIPTION
CYRF69213
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