CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 35

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Low Voltage Detect Control
Table 43. Low voltage Control Register (LVDCR) [0x1E3] [R/W]
POR Compare State
Table 44. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
This register controls the configuration of the Power on Reset/Low voltage Detection block
Bits 7:6
Bits 5:4
Bit 3
Bits 2:0
Bit #
Field
Read/Write
Default
This read-only register allows reading the current state of the Low voltage-Detection and Precision-Power-On-Reset compara-
Bits 7:2
Bit 1
Bit 0
VM[2:0]
000
001
010
011
100
101
110
Reserved
PORLEV[1:0]
This field controls the level below which the precision power-on-reset (PPOR) detector generates a reset
0 0 = 2.7V Range (trip near 2.6V)
0 1 = 3V Range (trip near 2.9V)
1 0 = 5V Range, >4.75V (trip near 4.65V). This setting must be used when operating the CPU above 12 MHz.
1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register
give the internal PPOR comparator state with trip point set to the 3V range setting
Reserved
VM[2:0]
This field controls the level below which the low voltage-detect trips—possibly generating an interrupt and the level
at which the Flash is enabled for operation
tors
Reserved
LVD
This bit is set to indicate that the low voltage-detect comparator has tripped, indicating that the supply voltage has
gone below the trip point set by VM[2:0] (See
0 = No low voltage-detect event
1 = A low voltage-detect has tripped
PPOR
This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply volt-
age is below the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1 = A precision-power-on-reset event has tripped
Reserved
Reserved
Reserved
Reserved
4.439
4.597
4.680
Min.
7
–
0
7
–
0
Reserved
LVD Trip Point (V)
Reserved
Reserved
Reserved
Reserved
Typical
6
–
0
4.48
4.64
4.73
6
–
0
Reserved
Reserved
Reserved
Reserved
5
–
0
R/W
4.528
4.689
4.774
Max.
5
0
Reserved
PORLEV[1:0]
.
Table
4
–
0
R/W
43)
4
0
Reserved
3
–
0
3
–
0
2
–
0
R/W
2
0
LVD
VM[2:0]
1
R
0
R/W
1
0
CYRF69213
(Table
PPOR
Page 35 of 77
0
R
0
R/W
0
0
44)
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