CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 38

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Pull up Enable
When set the pin has a 7K pull up to V
V3.3 enabled).
When clear, the pull up is disabled.
Output Enable
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
VREG Output/SPI Use
The P1.2 (VREG), P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI)
and P1.6 (SMISO) pins can be used for their dedicated functions
or for GPIO.
Table 49. P0.1 Configuration (P01CR) [0x06] R/W]
Document #: 001-07552 Rev. *D
This register is used to configure P0.1 In the CYRF69213, only 8 mA sink drive capability is available on this pin regardless of
the setting of the High Sink bit
Bit 7: Reserved
Read/Write
Default
Field
Bit #
Pull-Up Enable
TTL Threshold
Output Enable
Open Drain
3.3V Drive
High Sink
Port Data
Data In
Reserved
R/W
7
0
Int Enable
R/W
6
0
CC
(or VREG for ports with
Int Act Low
Figure 14. Block Diagram of a GPIO
R/W
5
0
TTL Thresh
VREG
VREG GND
R/W
4
0
To enable the pin for GPIO, clear the corresponding VREG
Output or SPI Use bit. The SPI function controls the output
enable for its dedicated function pins when their GPIO enable bit
is clear.
3.3V Drive
The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6
(SMISO) pins have an alternate voltage source from the voltage
regulator. If the 3.3V Drive bit is set a high level is driven from the
voltage regulator instead of from V
Setting the 3.3V Drive bit does not enable the voltage regulator.
That must be done explicitly by setting the VREG Enable bit in
the VREGCR Register
High Sink
R/W
3
0
VREG
Open Drain
V
V
CC
CC
R/W
(Table
2
0
GND
R
79).
UP
Pull up
Enable
CC
R/W
.
1
0
GPIO
CYRF69213
V
PIN
CC
Data Out
Output
Enable
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R/W
0
0
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