XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 13

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

X-Ref Target - Figure 9
V
consequently only one V
each bank. However, for correct operation, all V
the bank must be connected to the external reference
voltage source.
The V
device pinout tables. Within a given package, the number of
V
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
connected to the V
smaller devices, some V
not connect within the package. These unconnected pins
can be left unconnected externally, or, if necessary, they can
be connected to V
DS122 (v2.0) December 21, 2007
Product Specification
REF
REF
Figure 9: Virtex-II I/O Banks: Top View for Flip-Chip
REF
pins within a bank are interconnected internally, and
and V
CCO
pins for the largest device anticipated must be
and the V
CCO
R
pins can vary depending on the size of
CCO
Packages (FF & BF)
REF
REF
Bank 1
Bank 4
to permit migration to a larger device.
voltage and are not used for I/O. In
CCO
REF
pins for each bank appear in the
voltage can be used within
pins used in larger devices do
Bank 0
Bank 5
ds031_66_112900
REF
REF
pins in
REF
pins
www.xilinx.com
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bidirectional standards in the same bank:
•
•
•
•
•
The implementation tools enforce these design rules.
Combining output standards only. Output standards
with the same output V
combined in the same bank.
Combining input standards only. Input standards
with the same input V
can be combined in the same bank.
Combining input standards and output standards.
Input standards and output standards with the same
input V
combined in the same bank.
Combining bidirectional standards with input or
output standards. When combining bidirectional I/O
with other standards, make sure the bidirectional
standard can meet rules 1 through 3 above.
Additional rules for combining DCI I/O standards.
♦
♦
Compatible example:
Incompatible example:
Compatible example:
Incompatible example:
Incompatible example:
Compatible example:
Incompatible example:
No more than one Single Termination type (input or
output) is allowed in the same bank.
Incompatible example:
No more than one Split Termination type (input or
output) is allowed in the same bank.
Incompatible example:
CCO
SSTL2_I and LVDS_25_DCI outputs
SSTL2_I (output V
LVCMOS33 (output V
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
LVCMOS18 (input V
HSTL_I_DCI_18 (V
HSTL_IV_DCI_18 (V
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
HSTL_I_DCI_18 input (input V
HSTL_IV_DCI input and HSTL_III_DCI input
HSTL_I_DCI input and HSTL_II_DCI input
and output V
QPro Virtex-II 1.5V Platform FPGAs
CCO
CCO
CCO
CCO
REF
and input V
CCO
CCO
REF
CCO
requirement can be
= 2.5V) and
requirement can be
= 0.9V) and
= 1.5V) and
= 1.8V) inputs
= 1.1V) inputs
CCO
= 3.3V) outputs
CCO
= 2.5V) and
REF
= 1.8V)
requirements
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