XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 38

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Digital Clock Manager (DCM)
The Virtex-II DCM offers a wide range of powerful clock
management features:
•
•
•
The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations
during operation.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers
simultaneously (see
simultaneously drive general routing resources, including
routes to output buffers.
X-Ref Target - Figure 46
The DCM can be configured to delay the completion of the
Virtex-II configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
The DCM has the following general control signals:
•
•
•
DS122 (v2.0) December 21, 2007
Product Specification
Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
RST input
LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
STATUS output pins (active High): shown in
clock signal
control signal
Figure 46: Digital Clock Manager
R
pin:
resets the entire DCM.
Figure
CLKIN
CLKFB
RST
DSSEN
PSINCDEC
PSEN
PSCLK
46). All DCM clock outputs can
DCM
STATUS[7:0]
CLKFX180
CLK2X180
PSDONE
LOCKED
CLK180
CLK270
CLKDV
CLK2X
CLKFX
CLK90
CLK0
DS031_67_112900
Table
25.
www.xilinx.com
Table 25: DCM Status Pins
Clock De-Skew
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line.
Additional delay is introduced so that clock edges arrive at
internal registers and block RAMs simultaneously with the
clock edges arriving at the input clock pad. Alternatively,
external clocks, which are also de-skewed relative to the
input clock, can be generated for board-level routing. All
DCM output clocks are phase-aligned to CLK0 and,
therefore, are also phase-aligned to the input clock.
To achieve clock de-skew, the CLKFB input must be
connected, and its source must be either CLK0 or CLK2X.
CLKFB must always be connected, unless only the CLKFX
or CLKFX180 outputs are used and de-skew is not required.
Frequency Synthesis
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with
division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7,
7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.
The CLKFX and CLKFX180 outputs can be used to
produce clocks at the following frequency:
where M and D are two integers. Specifications for M and D
are provided under
M=4 and D=1, which results in a clock output frequency four
times faster than the clock input frequency (CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles (with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode).
Note:
mode.
FREQ
CLK2X and CLK2X180 are not available in high-frequency
Status Pin
CLKFX
0
1
2
3
4
5
6
7
= (M/D)
"DCM Timing
QPro Virtex-II 1.5V Platform FPGAs
×
FREQ
CLKIN
Parameters". By default,
Phase Shift Overflow
CLKFX Stopped
CLKIN Stopped
Function
N/A
N/A
N/A
N/A
N/A
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