XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 47

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Readback
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan modes.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
[Ref
Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a triple-
key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
device is not powered. Virtex-II devices can be configured
DS122 (v2.0) December 21, 2007
Product Specification
1].
R
BATT
pin, when the
www.xilinx.com
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II User Guide. Your local FAE can also
provide specific information on this feature.
Partial Reconfiguration
Partial reconfiguration of Virtex-II devices can be
accomplished in either Slave SelectMAP mode or
Boundary-Scan mode. Instead of resetting the chip and
doing a full configuration, new data is loaded into a specified
area of the chip, while the rest of the chip remains in
operation. Data is loaded on a column basis, with the
smallest load unit being a configuration “frame” of the
bitstream (device size dependent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
QPro Virtex-II 1.5V Platform FPGAs
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