XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 50

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult
system design.
V
V
Changes in V
should take place at a rate no faster than 10 mV per
millisecond. Techniques to help reduce jitter and period
distortion are provided in Xilinx Answer Record 13756,
available at www.support.xilinx.com.
V
V
Table 36: DC Input and Output Levels
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
3.
CCAUX
CCAUX
CCAUX
CCO
Input/Output
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
V
Tested according to the relevant specifications.
LVTTL and LVCMOS inputs have approximately 100 mV of hysteresis.
Standard
LVTTL
PCI33_3
PCI66_3
SSTL3 II
SSTL2 II
HSTL IV
HSTL III
SSTL3 I
SSTL2 I
OL
HSTL II
does not have excessive noise. Using simultaneously
HSTL I
PCI–X
GTLP
AGP
GTL
[Ref 2]
and V
can share a power plane with 3.3V V
powers critical resources in the FPGA. Thus,
is especially susceptible to power supply noise.
(1)
R
CCAUX
OH
for detailed information on power distribution
for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.
voltage outside of 200 mV peak to peak
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V
V
V
V
V
V
V
V
V
V
V
V
35% V
35% V
30% V
30% V
IL
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
V, Max
Note 2
0.8
0.8
0.7
– 0.05
– 0.15
– 0.15
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
– 0.2
– 0.2
– 0.2
CCO
CCO
CCO
CCO
CCO
V
V
V
65% V
65% V
50% V
50% V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note 2
V, Min
, but only if
2.0
2.0
1.7
+ 0.05
+ 0.15
+ 0.15
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.2
+ 0.2
+ 0.2
CCO
CCO
CCO
CCO
www.xilinx.com
V
IH
V
V
V
V
V
V
V
V
V
V
V
V
V
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
V, Max
Note 2
1.95
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to
determine the number of simultaneously switching outputs
allowed per bank at the package level.
DC Input and Output Levels
Values for V
Values for I
recommended operating conditions at the V
points. Only selected standards are tested. These are
chosen to ensure that all standards meet their
specifications. The selected standards are tested at
minimum V
levels shown. Other standards are sample tested.
3.6
3.6
2.7
1.7
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
V
V
10% V
10% V
V
V
10% V
OL
CCO
REF
REF
IL
REF
REF
V, Max
Note 2
V
0.4
0.4
0.4
0.4
0.4
0.6
0.4
0.4
0.4
0.4
0.4
and V
and I
OL
– 0.65
– 0.80
– 0.6
– 0.8
with the respective V
CCO
CCO
CCO
OH
IH
QPro Virtex-II 1.5V Platform FPGAs
are recommended input voltages.
are guaranteed over the
V
V
V
V
V
V
V
V
V
V
90% V
90% V
V
V
90% V
REF
REF
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
REF
REF
V, Min
Note 2
V
2.4
n/a
n/a
OH
+ 0.65
+ 0.80
+ 0.6
+ 0.8
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
CCO
CCO
CCO
OL
and V
Note 2
Note 2
Note 2
Note 2
15.2
mA
I
7.6
24
24
24
16
16
36
40
16
24
48
16
OL
8
8
OL
[Ref 3]
OH
and V
voltage
to
Note 2
Note 2
Note 2
Note 2
–15.2
OH
–7.6
mA
–24
–24
–24
–16
–16
–16
–16
I
n/a
n/a
–8
–8
–8
–8
OH
test
50