XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 8

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as an input and/or an output for single-ended I/Os. Two IOBs
can be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
IOB blocks are designed for high-performance I/Os,
supporting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
X-Ref Target - Figure 2
Note:
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and
outputs that support a wide variety of I/O signaling
standards. In addition to the internal supply voltage
(V
dependent on the I/O standard (see
supply voltage (V
the I/O standard used. For exact supply voltage absolute
maximum ratings, see
All of the user IOBs have fixed-clamp diodes to V
ground. As outputs, these IOBs are not compatible or
compliant with 5V I/O standards. As inputs, these IOBs are
not normally 5V tolerant, but can be used with 5V I/O
standards when external current-limiting resistors are used.
For more details, see the “5V Tolerant I/Os” Tech Topic at
http://www.xilinx.com.
Table 8, page 9
Controlled Impedance. See
(DCI)," page
DS122 (v2.0) December 21, 2007
Product Specification
CCINT
Differential I/Os must use the same clock.
Switch
Matrix
= 1.5V), output driver supply voltage (V
Figure 2: Virtex-II Input/Output Tile
R
15.
lists supported I/O standards with Digitally
CCAUX
"DC Input and Output Levels."
= 3.3V) is required, regardless of
"Digitally Controlled Impedance
PAD4
PAD3
PAD2
PAD1
IOB
IOB
IOB
IOB
Table
Differential Pair
Differential Pair
6). An auxiliary
DS031_30_101600
CCO
CCO
Figure
and to
) is
www.xilinx.com
2.
Table 6: Supported Single-Ended I/O Standards
Table 7: Supported Differential Signal I/O Standards
Notes:
1.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
AGP-2X/AGP
LVPECL_33
LDT_25
LVDS_33
LVDS_25
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
I/O Standard
Standard
V
voltage or the voltage seen at the I/O pad.
CCO
I/O
of GTL or GTLP should not be lower than the termination
Output
Output
Note 1
Note 1
V
V
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
3.3
CCO
QPro Virtex-II 1.5V Platform FPGAs
Input
V
Note 1
Note 1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Input
V
CCO
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
CCO
Input
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
Input
V
0.75
0.75
1.25
1.25
1.32
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
1.5
1.5
REF
490 mV to 1.22V
0.430 – 0.670
0.250 – 0.400
0.250 – 0.400
0.330 – 0.700
0.330 – 0.700
0.250 – 0.450
0.430 – 0.670
Voltage (V
Termination
Output
V
Board
0.75
0.75
1.25
1.25
OD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
1.5
1.5
TT
)
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