XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 35

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II devices.
Like the clock pads, eight global clock multiplexer buffers are
on the top edge of the device and eight are on the bottom.
X-Ref Target - Figure 39
Each global clock buffer can be driven by either the clock pad
to distribute a clock directly to the device, or the Digital Clock
Manager (DCM), discussed in
page
interconnects. The DCM has clock output(s) that can be
connected to global clock buffer inputs, as shown in
X-Ref Target - Figure 40
DS122 (v2.0) December 21, 2007
Product Specification
Figure 40: Virtex-II Clock Distribution Configurations
38. Each global clock buffer can also be driven by local
Clock Distribution
R
Figure 39: Virtex-II Clock Pads
Buffer
Clock
Clock
Pad
I
0
Virtex-II
Device
8 clock pads
8 clock pads
"Digital Clock Manager (DCM),"
Clock Distribution
Figure
CLKOUT
Buffer
DS031_43_101000
CLKIN
DCM
Clock
Clock
Pad
I
0
39.
DS031_42_101000
Figure
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40.
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks).
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock
distribution detail of the device prior to pin-locking and
floorplanning (see
Figure 42
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to
multiplex between two independent clock inputs (BUFGMUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in
X-Ref Target - Figure 41
The Virtex-II global clock buffer BUFG can also be
configured as a clock enable/disable circuit
well as a two-input clock multiplexer
description of these two options is provided below. Each of
them can be used in either of two modes, selected by
configuration: rising clock edge or falling clock edge.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX
primitives. The falling clock edge option uses the
BUFGCE_1 and BUFGMUX_1 primitives.
Figure
shows clock distribution in Virtex-II devices.
Figure 41: Virtex-II BUFG Function
41.
[Ref
I
QPro Virtex-II 1.5V Platform FPGAs
1]).
BUFG
DS031_61_101200
(Figure
O
44). A functional
(Figure
43), as
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