XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 69

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

QPro Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, with DCM
Table 56: Global Clock Setup and Hold for LVTTL Standard, with DCM
Global Clock Setup and Hold for LVTTL Standard, without DCM
Table 57: Global Clock Setup and Hold for LVTTL Standard, without DCM
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock
Input Signal for LVTTL Standard. For data input with
different standards, adjust the setup time delay by the
values shown in
Standard Adjustments," page
No Delay
Global Clock and IFF with DCM
Input Setup and Hold Time Relative to Global Clock
Input Signal for LVTTL Standard.
different standards, adjust the setup time delay by the
values shown in
Standard Adjustments," page
Full Delay
Global Clock and IFF
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative
to the Global Clock input signal with the slowest route and heaviest load.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative
to the Global Clock input signal with the slowest route and heaviest load.
IFF = Input Flip-Flop or Latch
These values are parametrically measured.
R
"IOB Input Switching Characteristics
"IOB Input Switching Characteristics
Description
Description
(2)
without DCM
55.
55.
(1)
For data input with
www.xilinx.com
T
PSDCM
T
PSFD
Symbol
Symbol
/T
/T
PHFD
PHDCM
XQ2V1000
XQ2V3000
XQ2V6000
XQ2V1000
XQ2V3000
XQ2V6000
Device
Device
QPro Virtex-II 1.5V Platform FPGAs
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.92/ 0.00
1.92/ 0.00
1.92/ 0.50
-5
-5
Speed Grade
Speed Grade
1.84/–0.76
1.96/–0.76
1.96/–0.76
2.21/ 0.00
2.21/ 0.00
2.21/ 0.50
-4
-4
Units
Units
ns
ns
ns
ns
ns
ns
69