XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 46

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II FPGA. Timing is similar to the Slave SerialMAP
mode except that CCLK is supplied by the Virtex-II FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In boundary-scan mode, dedicated pins are used for
configuring the Virtex-II device. The configuration is done
entirely through the IEEE 1149.1 Test Access Port (TAP).
Virtex-II device configuration using boundary scan is
Table 29: Virtex-II Configuration Mode Pin Settings
Table 30
each device.
Table 30: Virtex-II Bitstream Lengths
Configuration Sequence
The configuration of Virtex-II devices is a three-phase
process after Power On Reset or POR. POR occurs when
V
V
have been reached, the three-phase process begins.
First, the configuration memory is cleared. Next,
configuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless it is
delayed by the user. The INIT_B pin can be held Low using an
open-drain driver. An open-drain is required since INIT_B is a
bidirectional open-drain pin that is held Low by a Virtex-II
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
Notes:
1.
2.
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
Boundary Scan
CCINT
CCO
Configuration Mode
The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls
whether or not the pullups are used.
Daisy chaining is possible only in modes where Serial D
daisy chaining of downstream devices.
These values are only valid for STEPPING LEVEL 1.
Only STEPPING LEVEL 1 should be used with QPro devices.
XQ2V1000
XQ2V3000
XQ2V6000
(bank 4) is greater than 1.5V. Once the POR voltages
Device
is greater than 1.2V, V
lists the total number of bits required to configure
R
(1)
Number of Configuration Bits
CCAUX
M2
0
1
0
1
1
19,760,560
3,753,432
9,595,304
is greater than 2.5V, and
M1
0
1
1
1
0
M0
0
1
1
0
1
OUT
www.xilinx.com
is used. For example, in SelectMAP modes, the first device does NOT support
CCLK Direction
compliant with IEEE 1149.1-1993 standard and the new
IEEE 1532 standard for In-System Configurable (ISC)
devices. The IEEE 1532 standard is backward compliant
with the IEEE 1149.1-1993 TAP and state machine. The
IEEE Standard 1532 for In-System Configurable (ISC)
devices is intended to be programmed, reprogrammed, or
tested on the board via a physical and logical protocol.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.
FPGA device while the configuration memory is being cleared.
Extending the time that the pin is Low causes the configuration
sequencer to wait. Thus, configuration is delayed by
preventing entry into the phase where data is loaded.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as
necessary. One CCLK cycle later, the Global Write Enable
(GWE) signal is released. This permits the internal storage
elements to begin changing state in response to the logic
and the user clock.
The relative timing of these events can be changed via
configuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Out
N/A
Out
In
In
QPro Virtex-II 1.5V Platform FPGAs
Data Width
1
1
8
8
1
Serial D
Yes
Yes
No
No
No
OUT
(2)
46