XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 23

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

X-Ref Target - Figure 23
DS122 (v2.0) December 21, 2007
Product Specification
1 Shift Chain
in CLB
SRLC16
SRLC16
SRLC16
SRLC16
Figure 23: Cascadable Shift Register
DI
DI
R
DI
DI
MC15
MC15
MC15
MC15
SHIFTIN
SHIFTIN
D
D
D
D
SLICE S3
SLICE S2
IN
SHIFTOUT
OUT
FF
FF
FF
FF
CASCADABLE OUT
SLICE S1
SLICE S0
DI
SRLC16
SRLC16
SRLC16
SRLC16
DI
DI
SHIFTIN
DI
MC15
MC15
MC15
MC15
D
D
D
D
SHIFTOUT
SHIFTOUT
DS031_06_110200
FF
FF
FF
FF
CLB
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Multiplexers
Virtex-II function generators and associated multiplexers
can implement the following:
•
•
•
•
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in
page
one MUXF7 multiplexer and one MUXF8 multiplexer
(examples of multiplexers are shown in
can implement a 2:1 multiplexer.
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedicated
carry path and carry multiplexer (MUXCY) can also be used
to cascade function generators for implementing wide logic
functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a 2-bit
full adder to be implemented within a slice. In addition, a
dedicated AND (MULT_AND) gate (shown in
page
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices)
20) improves the efficiency of multiplier implementation.
24. Each CLB element has two MUXF6 multiplexers,
QPro Virtex-II 1.5V Platform FPGAs
Figure 25, page
[Ref
25.
Figure 17,
1]). Any LUT
Figure 24,
23