AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet
AGLE600V2-FGG484
Specifications of AGLE600V2-FGG484
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AGLE600V2-FGG484 Summary of contents
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... Six chip (main) and twelve quadrant global networks are available. 3. For devices supporting lower densities, refer to the November 2009 © 2010 Actel Corporation • Bank-Selectable I/O Voltages— Banks per Chip • Single-Ended 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2 5.0 V Input • ...
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IGLOOe Low Power Flash FPGAs 1 I/Os Per Package IGLOOe Devices ARM-Enabled IGLOOe Devices Package FG256 FG484 FG896 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ensure compliance with design and board ...
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IGLOOe Ordering Information _ AGLE3000 FG V2 Package Type 1.5 V only Part Number IGLOOe Devices AGLE600 = 600,000 Syst em Gat es AGLE3000 = 3,000,000 System Gates IGLOOe Devices with ...
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... C = Commercial temperature range: 0°C to 70°C ambient temperature Industrial temperature range: –40°C to 85°C ambient temperature. References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx AGLE600 – ...
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... Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109 Package Pin Assignments 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 IGLOOe Low Power Flash FPGAs ...
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... Cortex available for free from Actel for use in M1 IGLOOe FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not support AES decryption. Flash*Freeze Technology The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra- low power Flash*Freeze mode ...
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... Live at Power-Up The Actel flash-based IGLOOe devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOOe devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs ...
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... The versatility of the IGLOOe core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...
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IGLOOe Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG interface. ISP AES User Nonvolatile Decryption* FlashRom Figure 1-1 • IGLOOe Device Architecture Overview Flash*Freeze ...
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... LUT-3 CLK Y X3 CLR Figure 1-3 • VersaTile Configurations User Nonvolatile FlashROM Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • ...
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... Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents ...
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... Wide Range I/O Support Actel IGLOOe devices support JEDEC-defined wide range I/O operation. IGLOOe devices support both the JESD8-B specification, covering 3.0 V and 3.3 V supplies, for an effective operating range of 2 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1. 1.575 V. ...
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IGLOOe DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the ...
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... All parameters representing voltages are measured with respect to GND unless otherwise specified ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. ...
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Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature Programming Program Retention Product Grade Cycles (biased/unbiased) Commercial 500 Industrial 500 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated ...
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... JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see 2 on page 2-5 for more details) ...
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... Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Thermal Characteristics Introduction The temperature variable in Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. ...
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IGLOOe DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is θ θ . The thermal characteristics for θ ja temperature is 100°C. allowed for an 896-pin FBGA package at commercial temperature and in still air. Max. ...
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... Quiescent Supply Current Quiescent supply current (I ( VCC, VCCI, and VJTAG usage. Actel recommends using the PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • ...
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IGLOOe DC and Switching Characteristics Table 2-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode Current CCA Typical (25° Current CCI JTAG VCCI/VJTAG = 1.2 V (per bank) Typical (25°C) VCCI/VJTAG = 1.5 ...
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Power per I/O Pin Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 3 3.3 V LVCMOS Wide Range 3.3 V LVCMOS Wide ...
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IGLOOe DC and Switching Characteristics Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Single-Ended 3.3 V LVTTL/LVCMOS 4 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS ...
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... P Dynamic contribution for PLL AC13 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or ® SmartPower in Actel Libero Integrated Design Environment (IDE) software. Table 2-15 • Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOOe Devices, 1 ...
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... Dynamic PLL contribution AC13 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or SmartPower in Actel Libero IDE software. Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOOe V2 Devices, 1 Core Supply Voltage ...
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Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the ...
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IGLOOe DC and Switching Characteristics Combinatorial Cells Contribution— C-CELL C-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided ...
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Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means that this net switches at ...
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IGLOOe DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL 0.43 ns ICLKQ t = 0.47 ns ISUD Input LVTTL/LVCMOS 3.3 V Clock t = 1.10 ns ...
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PY PAD t = MAX DIN Vtrip PAD 50 GND PY (R) t PYS (R) DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example CLK I/O Interface (R), ...
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IGLOOe DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT t ...
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EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip VOL D 50 EOUT (R) VCC 50% EOUT t ZLS PAD Vtrip VOL Figure ...
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... High –0.3 VREF – 0.05 VREF + 0.05 High –0.3 VREF – 0.05 VREF + 0.05 3.6 High –0.3 VREF – 0.1 VREF + 0.1 High –0.3 VREF – 0.1 VREF + 0.1 High –0.3 VREF – 0.1 VREF + 0.1 IBIS Models, http://www.actel.com/download/ibis/default.aspx visio VOL VOH Max ...
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... VIH Min. Max. Min. Max VREF + 0.1 3.6 VREF + 0.2 3.6 VREF + 0.2 3.6 VREF + 0.2 3.6 VREF + 0.2 3.6 IBIS Models, http://www.actel.com/download/ibis/default.aspx IGLOOe Low Power Flash FPGAs 1 1 VOL VOH Max. Min 0.4 VCCI – 0 0.54 VCCI – 0. 0.35 VCCI – ...
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IGLOOe DC and Switching Characteristics Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS ...
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Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-22 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS ...
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IGLOOe DC and Switching Characteristics Table 2-23 • I/O AC Parameter Definitions Parameter t Data to Pad delay through the Output Buffer DP t Pad to Data delay through the Input Buffer with Schmitt trigger disabled PY t Data to ...
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Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings Std. Speed Grade, Commercial-Case Conditions: T Worst-Case VCCI (per standard) I/O Standard 3.3 V LVTTL / 12 12 High 3.3 V LVCMOS 3.3 V LVCMOS 100 µA 12 High 1, ...
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IGLOOe DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings Std. Speed Grade, Commercial-Case Conditions: T Worst-Case VCCI (per standard) I/O Standard 3.3 V LVTTL / 12 12 High 3.3 V LVCMOS 3.3 V LVCMOS ...
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... TBD 100 µA TBD Per PCI/PCI-X 25 specification IBIS models located O H spec IGLOOe Low Power Flash FPGAs Min. Max. Units (Ω) R (Ω) PULL-UP 300 150 TBD 200 100 225 112 224 112 TBD TBD 75 – on the Actel website ...
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... IBIS models located OLspec O H spec 1 R( (WEAK PULL-UP) (Ω) Minimum Maximum 110 110 k WEAK PULL-DOWN-MIN WEAK PULL-UP-MIN R e visio (Ω) R (Ω) PULL-UP 14 – 12 – 15 – the Actel website 2 R (WEAK PULL-DOWN) (Ω) Minimum Maximum 110 140 150 150 k at ...
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Table 2-29 • I/O Short Currents I OSH 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCIX ...
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... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t ...
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V DC Core Voltage Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade t DOUT 4 mA Std. 1.55 5.54 0.26 ...
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IGLOOe DC and Switching Characteristics 3.3 V LVCMOS Wide Range Table 2-39 • Minimum and Maximum DC Input and Output Levels 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Drive Strength Min. 3 Strength Option (V) 100 µA 2 ...
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Timing Characteristics 1 Core Voltage Table 2-41 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Equivalent Software Default Drive Drive Strength Speed 1 Strength ...
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V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-45 • Minimum and Maximum ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-47 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t DOUT 4 mA Std. ...
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V DC Core Voltage Table 2-49 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t t DOUT Std. 1.55 6. Std. ...
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IGLOOe DC and Switching Characteristics 1.8 V LVCMOS Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. ...
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Timing Characteristics 1 Core Voltage Table 2-53 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Speed Drive ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-55 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 ...
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V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-57 • Minimum ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-59 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t DOUT 2 mA Std. ...
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V DC Core Voltage Table 2-61 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t t DOUT Std. 1.55 8. Std. ...
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IGLOOe DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-63 ...
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Timing Characteristics 1 Core Voltage Table 2-65 • 1.2 LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t t DOUT Std. 1.55 9.92 0.26 2.09 ...
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... Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described VCCI for t ...
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Timing Characteristics 1 Core Voltage Table 2-70 • 3.3 V PCI/PCI-X – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Grade DOUT DP DIN Std. 0.97 2.38 0.18 Note: For specific junction ...
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IGLOOe DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 ...
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Timing Characteristics 1 Core Voltage Table 2-74 • 3.3 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade t t DOUT DP Std. ...
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IGLOOe DC and Switching Characteristics 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-76 ...
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V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-80 • Minimum and Maximum DC Input and Output Levels 3.3 V ...
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IGLOOe DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-84 • Minimum and Maximum DC Input ...
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HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-88 • Minimum and Maximum DC Input ...
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IGLOOe DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-92 • ...
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SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-96 • Minimum and Maximum DC Input and Output ...
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IGLOOe DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-100 • Minimum and ...
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SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-104 • Minimum and Maximum DC Input and Output ...
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IGLOOe DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-108 • Minimum and ...
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... Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional I/Os or tristates with the LVPECL standards ...
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IGLOOe DC and Switching Characteristics Table 2-112 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI Supply Voltage VOL Output Low Voltage VOH Output High Voltage 1 I Output Lower Current Output High Current ...
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... These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in ...
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IGLOOe DC and Switching Characteristics Table 2-116 • Minimum and Maximum DC Input and Output Levels DC Parameter Description VOH Output High Voltage VIL, VIH Input Low, Input High Voltages V Differential Output Voltage ODIFF V Output Common Mode Voltage ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-26 • Timing ...
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IGLOOe DC and Switching Characteristics Table 2-120 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 • Timing Model of ...
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IGLOOe DC and Switching Characteristics Table 2-121 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-28 • Input Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-122 • Input Data Register Propagation ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-123 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data Register ISUD ...
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Output Register 50% CLK 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-29 • Output Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-124 • Output Data Register Propagation Delays Commercial-Case Conditions: ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-125 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD ...
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Output Enable Register 50% 50% CLK t OESUD 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t OECLKQ Figure 2-30 • Output Enable Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-126 • ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-127 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-31 • Input DDR Timing Model Table 2-128 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t Data Setup ...
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IGLOOe DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-32 • Input DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-129 • Input DDR Propagation Delays Commercial-Case ...
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V DC Core Voltage Table 2-130 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR DDRICLKQ2 t Data Setup for Input DDR (negedge) DDRISUD1 t Data ...
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IGLOOe DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-33 • Output DDR Timing Model Table 2-131 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-34 • Output DDR Timing Diagram t t DDROHD2 DDROSUD2 DDROHD1 DDROCLKQ ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-132 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for Output DDR DDROCLKQ t Data_F Data Setup for Output DDR DDROSUD1 t ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOOe library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the and ProASIC3 Macro ...
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IGLOOe DC and Switching Characteristics Fanout = 4 Length = 1 VersaTile Length = 1 VersaTile Length = 1 VersaTile Length = 1 VersaTile 50 OUT GND VCC OUT Figure 2-36 • Timing Model and Waveforms 2- ...
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Timing Characteristics 1 Core Voltage Table 2-134 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Note: For specific junction temperature and voltage supply levels, refer to ...
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IGLOOe DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOOe library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-38 • Timing Model and Waveforms Timing Characteristics 1 Core Voltage Table 2-136 • Register Delays Commercial-Case Conditions: T ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-137 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for ...
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Global Resource Characteristics AGLE600 Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2- used to drive all D-flip-flops in the device. CCC Figure 2-39 • Example of Global Tree Use in an AGLE600 Device ...
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IGLOOe DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the ...
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V DC Core Voltage Table 2-140 • AGLE600 Global Resource Commercial-Case Conditions: T Parameter t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock RCKMPWH ...
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IGLOOe DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-142 • IGLOOe CCC/PLL Specification For IGLOOe Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning ...
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Table 2-143 • IGLOOe CCC/PLL Specification For IGLOOe V2 Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f 1 Serial Clock (SCLK) for Dynamic PLL Delay Increments in Programmable ...
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IGLOOe DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-41 • RAM Models 2- 92 RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA REN ...
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Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...
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IGLOOe DC and Switching Characteristics t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-44 • RAM Write, Output Retained (WMODE = 0) CLK ADD ...
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CLK1 ADD1 DI1 CCKH CLK2 WEN_B1 WEN_B2 A ADD2 DI2 D DO2 D (pass-through) DO2 D (pipelined) Figure 2-46 • Write Access after Write onto Same Address ...
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IGLOOe DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-47 • Read Access after Write onto Same Address ...
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CLK1 ADD1 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-48 • Write Access after Read onto Same Address t CKH CLK ...
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IGLOOe DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-144 • RAM4K9 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, ...
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Table 2-145 • RAM512X18 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REB_B, WEN_B Hold Time ENH t Input Data (DI) Setup Time DS t Input Data ...
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IGLOOe DC and Switching Characteristics Applies to 1 Core Voltage Table 2-146 • RAM4K9 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold ...
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Table 2-147 • RAM512X18 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REB_B, WEN_B Hold Time ENH t Input Data (DI) Setup Time DS t Input Data ...
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IGLOOe DC and Switching Characteristics FIFO Figure 2-50 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-51 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...
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IGLOOe DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...
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Timing Characteristics Applies to 1 Core Voltage Table 2-148 • FIFO Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t ...
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IGLOOe DC and Switching Characteristics Applies to 1 Core Voltage Table 2-149 • FIFO Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-56 • Timing Diagram Timing Characteristics Applies to 1 Core Voltage Table 2-150 • Embedded FlashROM Access Time Commercial-Case Conditions: T Parameter t Address Setup ...
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IGLOOe DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" section ...
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... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...
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...
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... Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner IGLOOe Low Power Flash FPGAs ...
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Package Pin Assignments 256-Pin FBGA Pin Number AGLE600 Function A1 GND A2 GAA0/IO00NDB0V0 A3 GAA1/IO00PDB0V0 A4 GAB0/IO01NDB0V0 A5 IO05PDB0V0 A6 IO10PDB0V1 A7 IO12PDB0V2 A8 IO16NDB0V2 A9 IO23NDB1V0 A10 IO23PDB1V0 A11 IO28NDB1V1 A12 IO28PDB1V1 A13 GBB1/IO34PDB1V1 A14 GBA0/IO35NDB1V1 A15 GBA1/IO35PDB1V1 A16 ...
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FBGA Pin Number AGLE600 Function G13 GCC1/IO50PPB2V1 G14 IO44NDB2V1 G15 IO44PDB2V1 G16 IO49NSB2V1 H1 GFB0/IO119NPB7V0 H2 GFA0/IO118NDB6V1 H3 GFB1/IO119PPB7V0 H4 VCOMPLF H5 GFC0/IO120NPB7V0 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO50NPB2V1 H13 GCB1/IO51PPB2V1 ...
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Package Pin Assignments 256-Pin FBGA Pin Number AGLE600 Function P9 IO82PDB5V0 P10 IO76NDB4V1 P11 IO76PDB4V1 P12 VMV4 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO67NDB3V1 R1 GEA1/IO102PDB6V0 R2 GEA0/IO102NDB6V0 R3 GNDQ R4 GEC2/IO99PDB5V2 R5 IO95NPB5V1 R6 IO91NDB5V1 R7 IO91PDB5V1 R8 ...
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... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner IGLOOe Low Power Flash FPGAs ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE600 Function A1 GND A2 GND A3 VCCIB0 A4 IO06NDB0V1 A5 IO06PDB0V1 A6 IO08NDB0V1 A7 IO08PDB0V1 A8 IO11PDB0V1 A9 IO17PDB0V2 A10 IO18NDB0V2 A11 IO18PDB0V2 A12 IO22PDB1V0 A13 IO26PDB1V0 A14 IO29NDB1V1 A15 IO29PDB1V1 A16 ...
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FBGA Pin Number AGLE600 Function C18 GND C19 NC C20 NC C21 NC C22 VCCIB2 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO05PDB0V0 D9 IO10PDB0V1 D10 IO12PDB0V2 D11 IO16NDB0V2 D12 IO23NDB1V0 ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE600 Function H13 VCCIB1 H14 VCCIB1 H15 VMV1 H16 GBC2/IO38PDB2V0 H17 IO37NDB2V0 H18 IO41NDB2V0 H19 IO41PDB2V0 H20 VCC H21 NC H22 NC J1 IO123NDB7V0 J2 IO123PDB7V0 IO124PDB7V0 J5 IO125PDB7V0 J6 ...
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FBGA Pin Number AGLE600 Function N8 VCCIB6 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB3 N16 IO54NPB3V0 N17 IO57NPB3V0 N18 IO55NPB3V0 N19 IO57PPB3V0 N20 NC N21 IO56NDB3V0 N22 IO58PDB3V0 IO111PDB6V1 ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE600 Function V3 GND V4 GEA1/IO102PDB6V0 V5 GEA0/IO102NDB6V0 V6 GNDQ V7 GEC2/IO99PDB5V2 V8 IO95NPB5V1 V9 IO91NDB5V1 V10 IO91PDB5V1 V11 IO83NDB5V0 V12 IO83PDB5V0 V13 IO77NDB4V1 V14 IO77PDB4V1 V15 IO69NDB4V0 V16 GDB2/IO69PDB4V0 V17 TDI V18 ...
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FBGA Pin Number AGLE3000 Function A1 GND A2 GND A3 VCCIB0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO16NDB0V1 A7 IO16PDB0V1 A8 IO18PDB0V2 A9 IO24PDB0V2 A10 IO28NDB0V3 A11 IO28PDB0V3 A12 IO46PDB1V0 A13 IO54PDB1V1 A14 IO56NDB1V1 A15 IO56PDB1V1 A16 IO64NDB1V2 A17 IO64PDB1V2 ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE3000 Function C18 GND C19 IO76PPB1V4 C20 IO88NDB2V0 C21 IO94PPB2V1 C22 VCCIB2 D1 IO293PDB7V2 D2 IO303NDB7V3 D3 IO305NDB7V3 D4 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO20PDB0V2 D9 IO22PDB0V2 D10 IO30PDB0V3 D11 ...
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FBGA Pin Number AGLE3000 Function H13 VCCIB1 H14 VCCIB1 H15 VMV1 H16 GBC2/IO84PDB2V0 H17 IO83NDB2V0 H18 IO100NDB2V2 H19 IO100PDB2V2 H20 VCC H21 VMV2 H22 IO105PDB2V2 J1 IO285NDB7V1 J2 IO285PDB7V1 J3 VMV7 J4 IO279PDB7V0 J5 IO283PDB7V1 J6 IO281PDB7V0 J7 IO287NDB7V1 ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE3000 Function N8 VCCIB6 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB3 N16 IO116NPB3V0 N17 IO132NPB3V2 N18 IO117NPB3V0 N19 IO132PPB3V2 N20 GNDQ N21 IO126NDB3V1 N22 IO128PDB3V1 P1 ...
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FBGA Pin Number AGLE3000 Function V3 GND V4 GEA1/IO234PDB6V0 V5 GEA0/IO234NDB6V0 V6 GNDQ V7 GEC2/IO231PDB5V4 V8 IO222NPB5V3 V9 IO204NDB5V1 V10 IO204PDB5V1 V11 IO195NDB5V0 V12 IO195PDB5V0 V13 IO178NDB4V3 V14 IO178PDB4V3 V15 IO155NDB4V0 V16 GDB2/IO155PDB4V0 V17 TDI V18 GNDQ V19 TDO ...
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... Package Pin Assignments 896-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx visio Ball Pad Corner ...
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FBGA AGLE3000 Pin Number Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function AC18 IO182PPB4V3 AC19 IO170NPB4V2 AC20 IO164NDB4V1 AC21 IO164PDB4V1 AC22 IO162PPB4V1 AC23 GND AC24 VCOMPLD AC25 IO150NDB3V4 AC26 IO148NDB3V4 AC27 GDA1/IO153PDB3V4 AC28 IO145NDB3V3 AC29 IO143NDB3V3 AC30 IO137NDB3V2 AD1 GND AD2 IO242NPB6V1 AD3 ...
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FBGA AGLE3000 Pin Number Function AF29 GNDQ AF30 GND AG1 IO238NPB6V0 AG2 VCC AG3 IO232NPB5V4 AG4 GND AG5 IO220PPB5V3 AG6 IO228PDB5V4 AG7 IO231NDB5V4 AG8 GEC2/IO231PDB5V4 AG9 IO225NPB5V3 AG10 IO223NPB5V3 AG11 IO221PDB5V3 AG12 IO221NDB5V3 AG13 IO205NPB5V1 AG14 IO199NDB5V0 AG15 IO199PDB5V0 ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function AK14 IO197PDB5V0 AK15 IO191NDB4V4 AK16 IO191PDB4V4 AK17 IO189NDB4V4 AK18 IO189PDB4V4 AK19 IO179PPB4V3 AK20 IO175NDB4V2 AK21 IO175PDB4V2 AK22 IO169NDB4V1 AK23 IO169PDB4V1 AK24 GND AK25 IO167PPB4V1 AK26 GND AK27 GDC2/IO156PPB4V0 AK28 GND AK29 ...
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FBGA AGLE3000 Pin Number Function D30 GBA2/IO82PPB2V0 E1 GND E2 IO303NPB7V3 E3 VCCIB7 E4 IO305PPB7V3 E5 VCC E6 GAC0/IO02NDB0V0 E7 VCCIB0 E8 IO06PPB0V0 E9 IO24NDB0V2 E10 IO24PDB0V2 E11 IO13NDB0V1 E12 IO13PDB0V1 E13 IO34NDB0V4 E14 IO34PDB0V4 E15 IO40NDB0V4 E16 IO49NDB1V1 ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function H11 IO18PDB0V2 H12 IO26NPB0V3 H13 IO28NDB0V3 H14 IO28PDB0V3 H15 IO38PPB0V4 H16 IO42NDB1V0 H17 IO52NDB1V1 H18 IO52PDB1V1 H19 IO62NDB1V2 H20 IO62PDB1V2 H21 IO70NDB1V3 H22 IO70PDB1V3 H23 GND H24 VCOMPLB H25 GBC2/IO84PDB2V0 H26 ...
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FBGA AGLE3000 Pin Number Function L26 IO87NDB2V0 L27 IO97PDB2V1 L28 IO101PDB2V2 L29 IO103PDB2V2 L30 IO119NDB3V0 M1 IO282NDB7V1 M2 IO282PDB7V1 M3 IO292NDB7V2 M4 IO292PDB7V2 M5 IO283NDB7V1 M6 IO285PDB7V1 M7 IO287PDB7V1 M8 IO289PDB7V1 M9 IO289NDB7V1 M10 VCCIB7 M11 VCC M12 GND ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function R11 VCC R12 GND R13 GND R14 GND R15 GND R16 GND R17 GND R18 GND R19 GND R20 VCC R21 VCCIB2 R22 GCC0/IO112NDB2V3 R23 GCB2/IO116PDB3V0 R24 IO118PDB3V0 R25 IO111PPB2V3 R26 ...
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FBGA AGLE3000 Pin Number Function V26 IO126NDB3V1 V27 IO129NDB3V1 V28 IO127NDB3V1 V29 IO125NDB3V1 V30 IO123PDB3V1 W1 IO266NDB6V4 W2 IO262NDB6V3 W3 IO260NDB6V3 W4 IO252NDB6V2 W5 IO251NDB6V2 W6 IO251PDB6V2 W7 IO255NDB6V2 W8 IO249PPB6V1 W9 IO253PDB6V2 W10 VCCIB6 W11 VCC W12 GND ...
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Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the IGLOOe datasheet. Revision July 2010 The versioning system for datasheets has been changed. Datasheets are assigned a revision number ...
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... I/O Standards" Revision 5 (Oct 2008) The Quiescent Current values in updated. Product Brief v1.2 Revision 4 (Jul 2008 result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change Product Brief v1.1 1 and Switching Characteristics Advance v0 ...
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Revision Revision 3 (cont’d) The table notes for Flash*Freeze Mode*, Mode (VCC = 0 Shutdown Mode (VCC, VCCI = 0 V)* P and P DC6 DC7 the table note for Shutdown Mode (VCC, VCCI = 0 Note 2 of Table ...
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... I/O voltages in the and "Pro I/Os with Advanced I/O Standards" section Revision 0 (Jan 2008) This document was previously in datasheet Advance v0. result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700096-001-0. Advance v0.4 The Table 1 • ...
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Revision Advance v0.4 Table 3-99 • Minimum and Maximum DC Input and Output Levels was updated. (continued) Table 3-136 • JTAG 1532 and Table 3-135 • JTAG 1532 were updated. The "484-Pin FBGA" table for AGLE3000 is new. The "896-Pin ...
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... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...
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... Fax +44 (0) 1276 607 540 © Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. ...