AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 68

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AGLE600V2-FGG484

Manufacturer Part Number
AGLE600V2-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGLE600V2-FGG484

Processor Series
AGLE600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
270
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLE600V2-FGG484
Manufacturer:
Actel
Quantity:
135
Part Number:
AGLE600V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOOe DC and Switching Characteristics
Table 2-84 • Minimum and Maximum DC Input and Output Levels
Figure 2-16 • AC Loading
Table 2-85 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-86 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage
Table 2-87 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage
2- 54
2.5 V GTL+
Drive
Strength
33 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
*
Speed Grade
Std.
Note:
Speed Grade
Std.
Note:
Measuring point = V
is larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The V
Timing Characteristics
Min.
Commercial-Case Conditions: T
Worst-Case VCCI = 2.3 V VREF = 1.0 V
Commercial-Case Conditions: T
Worst-Case VCCI = 2.3 V VREF = 1.0 V
–0.3
V
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Input High (V)
VREF + 0.1
VIL
t
t
VREF – 0.1
trip
DOUT
0.98
DOUT
1.55
. See
Max.
V
Table 2-22 on page 2-23
1.97
2.23
t
t
DP
DP
VREF + 0.1
Measuring Point* (V)
0.19
0.26
t
t
Min.
DIN
DIN
V
VIH
Test Point
1.29
1.55
1.0
t
t
J
J
PY
PY
= 70°C, Worst-Case VCC = 1.425 V,
= 70°C, Worst-Case VCC = 1.14 V,
Max.
3.6
V
GTL+
for a complete table of trip points.
t
t
0.67
1.10
EOUT
EOUT
R e visio n 8
Max.
VOL
0.6
V
V
TT
VREF (typ.) (V)
25
2.00
2.28
10 pF
t
t
ZL
ZL
VOH I
Min.
V
1.0
CCI
1.84
2.11
t
Table 2-6 on page 2-6
t
Table 2-7 on page 2-6
mA mA
ZH
ZH
OL
33 33
pin should be connected to 2.5 V.
I
OH
t
t
LZ
LZ
VTT (typ.) (V)
Max.
I
mA
169
OSH
t
t
HZ
HZ
1.5
3
5.63
8.08
t
t
ZLS
ZLS
Max.
mA
I
124
for derating values.
for derating values.
OSL
3
7.91
t
5.47
t
ZHS
ZHS
C
µA
I
LOAD
IL
10 10
1
4
10
µA
I
IH
Units
Units
(pF)
2
ns
ns
4

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