AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 51

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AGLE600V2-FGG484

Manufacturer Part Number
AGLE600V2-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGLE600V2-FGG484

Processor Series
AGLE600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
270
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLE600V2-FGG484
Manufacturer:
Actel
Quantity:
135
Part Number:
AGLE600V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-45 • Minimum and Maximum DC Input and Output Levels
Figure 2-8 • AC Loading
Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads
2.5 V LVCMOS
Drive
Strength
4 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < V
is the input leakage current per I/O pin over recommended operating conditions V
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Test Point
Datapath
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
V
trip
VIL
. See
Input High (V)
Max.
0.7
0.7
0.7
0.7
0.7
V
Table 2-22 on page 2-23
2.5
35 pF
Min.
1.7
1.7
1.7
1.7
1.7
V
VIH
Enable Path
Max.
Measuring Point* (V)
Test Point
3.6
3.6
3.6
3.6
3.6
V
R = 1 k
for a complete table of trip points.
Max.
VOL
1.2
0.7
0.7
0.7
0.7
0.7
V
R e v i s i o n 8
VOH
Min.
1.7
1.7
1.7
1.7
1.7
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
V
mA mA
I
OL
12 12
16 16
24 24
4
8
V
REF
HZ
I
OH
ZH
4
8
/ t
(typ.) (V)
/ t
LZ
HZ
LZ
ZHS
Max.
mA
/ t
I
/ t
IH
OSH
169
16
32
65
83
IGLOOe Low Power Flash FPGAs
ZL
ZH
/ t
< V
3
ZL
/ t
/ t
IN
ZLS
ZHS
/ t
< V
ZLS
IN
CCI
Max.
mA
I
OSL
124
C
18
37
74
87
< V
. Input current is
LOAD
3
IL
5
.
(pF)
µA
I
IL
10
10
10
10
10
1
4
µA
I
2- 37
IH
10
10
10
10
10
2
4

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