AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 85

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-29 • Output Register Timing Diagram
Table 2-124 • Output Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
Enable
DOUT
CLK
Preset
Clear
Data_out
For specific junction temperature and voltage supply levels, refer to
Output Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
1.5 V DC Core Voltage
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
50%
J
= 70°C, Worst-Case VCC = 1.425 V
50%
t
OWPRE
t
Description
OPRE2Q
50%
50%
R e v i s i o n 8
t
t
ORECPRE
OCLR2Q
50%
50%
t
OWCLR
50%
50%
50%
Table 2-6 on page 2-6
t
ORECCLR
50%
IGLOOe Low Power Flash FPGAs
t
OCKMPWH
t
50%
OREMPRE
t
50%
OCKMPWL
for derating values.
1.00
0.51
0.70
0.00
1.34
1.34
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
0.00
t
OREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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