AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 45

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-33 • Minimum and Maximum DC Input and Output Levels
Figure 2-7 • AC Loading
Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
4 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = Vtrip. See
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VI
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Test Point
Datapath
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
V
VIL
Input High (V)
Max.
0.8
0.8
0.8
0.8
0.8
V
Table 2-22 on page 2-23
3.3
35 pF
Min.
V
2
2
2
2
2
VIH
Measuring Point* (V)
Max.
Enable Path
Test Point
3.6
3.6
3.6
3.6
3.6
V
R = 1 k
1.4
Max.
VOL
for a complete table of trip points.
0.4
0.4
0.4
0.4
0.4
V
R e v i s i o n 8
VOH
Min.
2.4
2.4
2.4
2.4
2.4
R to VCCI for t
R to GND for t
V
35 pF for t
5 pF for t
mA mA
I
OL
12 12
16 16
24 24
VREF (typ.) (V)
4
8
HZ
I
OH
ZH
4
8
/ t
–
/ t
LZ
HZ
LZ
ZHS
Max.
I
mA
/ t
/ t
103
132
268
OSH
25
51
IGLOOe Low Power Flash FPGAs
ZL
ZH
/ t
3
ZL
/ t
/ t
ZLS
ZHS
/ t
ZLS
Max.
mA
I
109
127
181
OSL
27
54
C
LOAD
3
5
L
.
(pF)
µA
I
IL
10
10
10
10
10
1
4
µA
I
2- 31
IH
10
10
10
10
10
2
4