AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 74

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AGLE600V2-FGG484

Manufacturer Part Number
AGLE600V2-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGLE600V2-FGG484

Processor Series
AGLE600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
270
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLE600V2-FGG484
Manufacturer:
Actel
Quantity:
135
Part Number:
AGLE600V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOOe DC and Switching Characteristics
Table 2-108 • Minimum and Maximum DC Input and Output Levels
Figure 2-22 • AC Loading
Table 2-109 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-110 • SSTL 3 Class II – Applies to 1.5 V DC Core Voltage
Table 2-111 • SSTL 3 Class II – Applies to 1.2 V DC Core Voltage
2- 60
SSTL3 Class II
Drive Strength
21 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
Note:
Speed Grade
Std.
Note:
Speed Grade
Std.
Note:
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Measuring point = Vtrip. See
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class
II. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.5 V
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Min.
–0.3 VREF – 0.2 VREF + 0.2
V
Input High (V)
VREF + 0.2
t
t
DOUT
0.98
DOUT
1.55
VIL
Max.
V
1.86
2.12
t
t
DP
DP
Table 2-22 on page 2-23
Measuring Point* (V)
0.19
0.26
t
t
DIN
DIN
Min.
Test Point
V
VIH
1.09
1.32
1.5
t
t
J
PY
PY
= 70°C, Worst-Case VCC = 1.14 V,
Max.
3.6
V
SSTL3
Class II
t
t
0.67
1.10
25
EOUT
EOUT
R e visio n 8
Max.
VOL
0.5
for a complete table of trip points.
V
VREF (typ.) (V)
V
1.89
2.16
TT
t
t
ZL
ZL
25
VCCI – 0.9 21 21
30 pF
1.5
VOH
Min.
V
1.58
1.89
t
Table 2-6 on page 2-6
t
Table 2-7 on page 2-6
ZH
ZH
mA mA
I
OL
t
t
LZ
LZ
VTT (typ.) (V)
I
OH
t
t
1.485
HZ
HZ
Max.
I
mA
103
OSH
5.52
7.97
t
t
3
ZLS
ZLS
for derating values.
for derating values.
Max.
mA
I
109
OSL
t
5.21
t
7.70
C
ZHS
ZHS
LOAD
3
30
µA
I
IL
10 10
(pF)
Units
Units
1
ns
ns
4
µA
I
IH
2
4

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