AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 94

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOOe DC and Switching Characteristics
Table 2-132 • Output DDR Propagation Delays
Table 2-133 • Output DDR Propagation Delays
2- 80
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
DDOMAX
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
J
J
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.14 V
Description
Description
R e visio n 8
Table 2-6 on page 2-6
Table 2-7 on page 2-6
for derating values.
for derating values.
1.07
0.67
0.00
0.00
1.38
0.00
0.23
0.19
0.31
0.28
1.60
1.16
0.00
0.00
1.99
0.00
0.24
0.19
0.31
0.28
Std.
0.67
Std.
1.09
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns