MT47H32M16HR-3:F Micron Technology Inc, MT47H32M16HR-3:F Datasheet - Page 38

• Manufacturer Part Number: MT47H32M16HR-3:F
• Description: IC DDR2 SDRAM 512MBIT 3NS 84FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3:F

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1466

Notes:
10. MIN (
11.
12. The period jitter (
13. The half-period jitter (
14. The cycle-to-cycle jitter (
15. The cumulative jitter error (
16. JEDEC specifies using
17. This parameter is not referenced to a specific voltage level but is specified when the device output is no longer
1. All voltages are referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load (see Figure 14 (page 48)).
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is, the receiver will effective-
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode (see Figure 77 (page 123)), precharge
8. The clock’s
9. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate
voltage levels, but the related specifications and the operation of the device are warranted for the full voltage
range specified. ODT is disabled for all measurements that are not ODT-specific.
tions are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input
signals used to test the device is 1.0 V/ns for signals in the range between V
1.0 V/ns may require the timing parameters to be derated as specified.
ly switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal
does not ring back above [below] the DC input LOW [HIGH] level).
power-down mode, or system reset condition (see Reset (page 124)). SSC allows for small deviations in operating
frequency, provided the SSC guidelines are satisfied.
rate allowed (except for a deviation due to allowed clock jitter). Input clock jitter is allowed provided it does not
exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature.
spread spectrum at a sweep rate in the range 8–60 kHz with an additional one percent
spread spectrum may not use a clock rate below
device. The clock’s half period must also be of a Gaussian distribution;
or without clock jitter and with or without duty cycle jitter.
consecutive CK falling edges.
half period limits (
t
of
in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During
DLL lock time, the jitter values should be 20 percent less those than noted in the table (DLL locked).
cumulatively can not exceed
fies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent
less than those noted in the table (DLL locked).
consecutively accumulate away from the average clock over any number of clock cycles.
less derating by allowing
driving (
HP (MIN) is the lesser of
t
CL (ABS) MIN and
t
CL,
t
RPST) or beginning to drive (
t
CH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven to the
t
CK (AVG) is the average clock over any 200 consecutive clocks and
DD
t
t
JITper) is the maximum deviation in the clock period from the average or nominal clock allowed
tests may use a V
CH [ABS],
DD
t
t
CH (ABS) MIN.
t
ERR
JITdty) applies to either the high pulse of clock or the low pulse of clock; however, the two
, and electrical AC and DC characteristics may be conducted at nominal reference/supply
t
t
JITcc) is the amount the clock period can deviate from one cycle to the next. JEDEC speci-
t
CL and
6–10per
ERR
t
ERR
t
t
t
CL [ABS]) are not violated.
JITper.
5per
CH limits may be exceeded if the duty cycle jitter is small enough that the absolute
SS
nper
when derating clock-related output timing (see notes 19 and 48). Micron requires
t
.
CH actually applied to the device CK and CK# inputs; thus,
to be used.
IL
), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount of clock time allowed to
-to-V
t
RPRE).
IH
swing of up to 1.0V in the test environment, and parameter specifica-
t
CK (AVG) MIN or above
t
CH (AVG) and
t
CH (AVG) and
t
CK (AVG) MAX.
t
IL(AC)
CL (AVG) are the average of any 200
t
CK (AVG) MIN is the smallest clock
and V
t
CL (AVG) must be met with
IH(AC)
t
CK (AVG); however, the
. Slew rates other than
t
HP (MIN) ≥ the lesser