MT47H32M16HR-3:F Micron Technology Inc, MT47H32M16HR-3:F Datasheet - Page 40

• Manufacturer Part Number: MT47H32M16HR-3:F
• Description: IC DDR2 SDRAM 512MBIT 3NS 84FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3:F

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1466

31. V
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address:
34. This is applicable to READ cycles only. WRITE cycles generally require additional time due to
35. READs and WRITEs with auto precharge are allowed to be issued before
36. When a single-bank PRECHARGE command is issued,
37. This parameter has a two clock minimum requirement at any
38. The
39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-bit prefetch begins to
40.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equates to an average refresh
42.
43.
44.
using Table 33 (page 63). Single-ended DQS data timing is referenced at DQS crossing V
values for a single-ended DQS strobe are listed in Table 34 (page 63)–Table 36 (page 64) on Table 34
(page 63), Table 35 (page 64), and Table 36 (page 64); listed values are already derated for slew rate varia-
tions and converted from baseline values to V
only) are equivalent to the baseline values of
t
rising signal and V
falling signal. If the command/address slew rate is not equal to 1 V/ns, then the baseline values must be derated
by adding the values from Table 29 (page 57) and Table 30 (page 58).
charge.
out feature is supported in DDR2 SDRAM.
CHARGE (ALL) command is issued, regardless of the number of banks open. For 8-bank devices (≥1Gb),
=
be issued in a given
when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the
READ so that data will output CL later. This parameter is only applicable when
cies faster than 533 MHz when
to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until
(MIN) has been satisfied.
t
t
ple, -37E at
4 + (4) clocks = 8 clocks.
rate of 7.8125µs (commercial) or 3.9607µs (industrial and automotive). To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial and automotive).
The JEDEC
t
moved in a system RESET condition (see Reset (page 124)).
t
t
remain at the valid input level the entire time it takes to achieve the three clocks of registration. Thus, after any
CKE transition, CKE may not transition from its valid level during the time period of
IS
DAL = (nWR) + (
CK refers to the application clock period; nWR refers to the
DELAY is calculated from
ISXR is equal to
CKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must
IL
t
b
RP (MIN) +
/V
,
t
t
IH
FAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-ACTIVATE commands may
IH
DDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification (page 54).
b
, are the JEDEC-defined values, referenced from the logic trip points.
t
RFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is allowed.
t
CK = 3.75ns with
t
CK (AVG) (Table 12 (page 31) lists
t
t
RP/
IS and is used for CKE setup time during self refresh exit, as shown in Figure 67 (page 115).
IL(AC)
t
t
FAW (MIN) period.
CK). Each of these terms, if not already an integer, should be rounded up to the next integer.
for a falling signal, while
t
IS +
t
WR programmed to four clocks would have
t
t
CK +
RTP = 7.5ns. If
t
IH so that CKE registration LOW is guaranteed prior to CK, CK# being re-
t
RRD (MIN) restriction still applies.
t
REF
IS
t
RTP/(2 ×
b
t
,
t
RP [MIN] +
values.
IH
t
IH
b
b
t
is referenced from V
RP timing applies.
at V
t
CK) ≤ 1, then equation AL + BL/2 applies.
t
IS
REF
a
t
,
t
CK [AVG] MIN).
WR parameter stored in the MR9–MR11. For exam-
t
t
when the slew rate is 1 V/ns. The baseline values,
CK.
IH
a
and
t
IS
t
b
t
RPA timing applies when the PRE-
RAS (MIN) is satisfied because
,
IL(DC)
t
t
DAL = 4 + (15ns/3.75ns) clocks =
IH
b
t
IS
. The
for a rising signal and V
t
RTP/(2 ×
b
is referenced from V
t
t
IS
IS + 2 ×
a
,
REF
t
t
IH
CK) > 1, such as frequen-
. The correct timing
a
t
values (for reference
WR during auto pre-
t
CK +
t
RAS (MIN) has
t
IH.
IH(AC)
IH(DC)
t
t
RPA (MIN)
RAS lock-
t
RAS
for a
for a