MT47H32M16HR-3:F Micron Technology Inc, MT47H32M16HR-3:F Datasheet - Page 97

• Manufacturer Part Number: MT47H32M16HR-3:F
• Description: IC DDR2 SDRAM 512MBIT 3NS 84FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3:F

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1466

READ with Auto Precharge
Table 42: READ Using Concurrent Auto Precharge
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
From Command (Bank n)
READ with auto precharge
If A10 is high when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-
ded
edge, the start point of the auto precharge operation will be delayed until
satisfied. If
auto precharge operation will be delayed until
nal precharge is pushed out by
charge happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (
auto precharge to the next ACTIVATE command is AL + 2 clocks + (
term (
tion can also be used: AL + BL/2 - 2CK + (
precharge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in Ta-
ble 42. Examples of READ with precharge and READ with auto precharge with applica-
ble timing requirements are shown in Figure 51 (page 98) and Figure 52 (page 99),
respectively.
t
WRITE or WRITE with auto precharge
RAS (MIN) and
READ or READ with auto precharge
t
RTP +
PRECHARGE or ACTIVATE
To Command (Bank m)
t
RTP (MIN) is not satisfied at this rising clock edge, the start point of the
t
RP)/
t
t
CK is always rounded up to the next integer. A general purpose equa-
RTP +
t
RTP are satisfied. If
t
RP)/
97
t
t
CK. When BL = 8, the minimum time from READ with
RTP,
t
RP starts at the point where the internal pre-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
RAS (MIN) is not satisfied at this rising clock
RTP +
512Mb: x4, x8, x16 DDR2 SDRAM
(with Concurrent Auto Precharge)
t
RTP (MIN) is satisfied. When the inter-
t
RP)/
Minimum Delay
t
CK. In any event, the internal
(BL/2) + 2
BL/2
1
© 2004 Micron Technology, Inc. All rights reserved.
t
RTP +
t
t
RAS (MIN) is
RP)/
t
CK. The
READ
Units
t
t
t
CK
CK
CK