MT47H32M16HR-3:F Micron Technology Inc, MT47H32M16HR-3:F Datasheet - Page 95

• Manufacturer Part Number: MT47H32M16HR-3:F
• Description: IC DDR2 SDRAM 512MBIT 3NS 84FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3:F

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1466

Figure 47: READ Interrupted by READ
Figure 48: READ-to-WRITE
READ with Precharge
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
CK#
A10
CK#
DQ
DQ
CK
CK
READ 1
Valid 4
ACT n
T0
T0
Notes:
Notes:
READ n
T1
t CCD
NOP 2
T1
CL = 3 (AL = 0)
t RCD = 3
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and
t
prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time
from the actual READ (AL after the READ command) to PRECHARGE command. For
BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command.
Following the PRECHARGE command, a subsequent command to the same bank can-
RTP.
1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is-
3. Interrupting READ command must be issued exactly 2 ×
4. READ command can be issued to any valid bank and row address (READ command at T0
5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal
1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal
AL = 2
NOP
T2
sued to banks used for READs at T0 and T2.
and T2 can be either same bank or different bank).
terrupting READ command.
t
READ 3
Valid 5
Valid 4
RTP is the minimum time from the rising clock edge that initiates the last 4-bit
T2
NOP
T3
RL = 5
NOP 2
T3
CL = 3 (AL = 0)
DO
NOP
T4
CL = 3
DO
t
AC,
Valid
T4
WRITE
DO
95
t
T5
DQSCK, and
DO
Valid
T5
NOP
T6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DO
DO
n
t
DQSQ.
512Mb: x4, x8, x16 DDR2 SDRAM
n + 1
DO
WL = RL - 1 = 4
DO
NOP
Valid
T7
T6
n + 2
DO
DO
n + 3
DO
DO
NOP
T8
Valid
T7
t
CK from previous READ.
DO
Transitioning Data
Transitioning Data
© 2004 Micron Technology, Inc. All rights reserved.
NOP
T9
DI
n
DO
t
AC,
Valid
T8
n + 1
DI
DO
t
DQSCK, and
NOP
T10
n + 2
DI
DO
n + 3
Valid
DI
T9
Don’t Care
Don’t Care
NOP
T11
READ
t
DQSQ.