KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 103

• Manufacturer Part Number: KSZ8893FQL-FX
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893FQL-FX

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 1000Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3273

Micrel, Inc.
Examples:
Additional MIB Counter Information
“Per Port” MIB counters are designed as “read clear.” These counters will be cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity;
therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are 160
registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes.
It is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
October 2007
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Then
Then,
Then
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x0e
Read reg. 128 (0x80), overflow bit [31]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x2e
Read reg. 128 (0x80), overflow bit [31]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Write to reg. 121 (0x79) with 0x1d
Write to reg. 122 (0x7A) with 0x00
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
valid bit [30]
counter bits [29:24]
counter bits [29:24]
valid bit [30]
103
// Read MIB counters selected
// Trigger the read operation
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
// Read MIB counter selected
// Trigger the read operation
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
// Read MIB counter selected
// Trigger the read operation
M9999-101607-1.3
KSZ8893FQL