KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 41

• Manufacturer Part Number: KSZ8893FQL-FX
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893FQL-FX

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 1000Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3273

Micrel, Inc.
MII Management (MIIM) Interface
The KSZ8893FQL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8893FQL. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
The MIIM Interface can operate up to a maximum clock speed of 5 MHz.
The following table depicts the MII Management Interface frame format.
Serial Management Interface (SMI)
The SMI is the KSZ8893FQL non-standard MIIM interface that provides access to all KSZ8893FQL configuration
registers. This interface allows an external device to completely monitor and control the states of the KSZ8893FQL.
The SMI interface consists of the following:
The following table depicts the SMI frame format.
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence, can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8893FQL registers 0-141 (0x00 – 0x8D), the following applies:
October 2007
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Read
Write
Read
Write
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893FQL device.
Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM
registers [29, 31].
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893FQL device.
Access to all KSZ8893FQL configuration registers. Register access includes the Global, Port and Advanced
Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers [0:5] and custom
MIIM registers [29, 31].
PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
Registers are 8 data bits wide.
–
–
Preamble
Preamble
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
32 1’s
32 1’s
32 1’s
32 1’s
Start of
Start of
Frame
Frame
01
01
01
01
Table 13. Serial Management Interface (SMI) Frame Format
Read/Write
Table 12. MII Management Interface Frame Format
Read/Write
OP Code
OP Code
10
01
00
00
Bits [4:0]
Address
Bits [4:0]
Address
AAAAA
AAAAA
1xRRR
0xRRR
PHY
PHY
41
Bits [4:0]
Address
Bits [4:0]
Address
RRRRR
RRRRR
RRRRR
RRRRR
REG
REG
TA
TA
Z0
10
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Bits [15:0]
Bits [15:0]
Data
Data
M9999-101607-1.3
KSZ8893FQL
Idle
Idle
Z
Z
Z
Z